MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 286
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Synchronous DRAM Controller Module
Note that in synchronous operation, burst mode and address incrementing during burst cycles are
controlled by the DRAM controller. Thus, instead of the SDRAM enabling its internal burst incrementing
capability, the processor controls this function. This means that the burst function that is enabled in the
mode register of SDRAMs must be disabled when interfacing to the processor.
Figure 15-6
delay (t
data out), this value is also 2 system clock cycles. Notice that
A
Figure 15-7
SRAS-to-SCAS delay (t
and a burst write cycle completes two cycles sooner than a burst read cycle with the same t
bus cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-to-
completes.
15-14
PALL
SDRAM_CS[0] or [1]
RCD
command is executed one cycle after the last data transfer.
) of 2 system clock cycles. Because t
CLKOUT
DRAMW
shows a burst read operation. In this example, DACR[CASL] = 01 for an SRAS-to-SCAS
shows the burst write operation. In this example, DACR[CASL] = 01, which creates an
A[23:0]
D[31:0]
BS[3:0]
SRAS
SCAS
RCD
t
RCD
ACTV
Row
) of 2 system clock cycles. Note that data is available upon SCAS assertion
= 2
Figure 15-6. Burst Read SDRAM Access
NOP
Column Column Column
READ
t
CASL
RCD
READ
= 2
is equal to the read CAS latency (SCAS assertion to
READ
NOP
Column
s are executed until the last data is read.
READ
NOP
t
EP
NOP
Freescale Semiconductor
PALL
RCD.
ACTV
The next
delay
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