MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 54

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

ColdFire Core
2.2.9
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
2-8
2.2.10
The memory base address registers are used to specify the base address of the internal SRAM and flash
modules and indicate the types of references mapped to each. Each base address register includes a base
address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base
address of the on-chip flash, and RAMBAR determines the base address of the on-chip RAM. For more
information, refer to
“Flash Base Address Register
Field
10–8
CCR
7–0
Reset
BDM: 0x80E (SR)
15
14
13
12
11
M
T
S
I
W
R
Trace enable. When set, the processor performs a trace exception after every instruction.
Reserved, must be cleared.
Supervisor/user state.
0 User mode
1 Supervisor mode
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
Reserved, must be cleared.
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
Refer to
15
T
0
Status Register (SR)
Memory Base Address Registers (RAMBAR, FLASHBAR)
14
Section 2.2.4, “Condition Code Register
0
0
Section 5.3.1, “SRAM Base Address Register (RAMBAR)”
13
S
1
System Byte
12
M
0
(FLASHBAR)”.
11
0
0
Table 2-3. SR Field Descriptions
Figure 2-8. Status Register (SR)
10
1
1
9
I
(CCR)”.
Description
1
8
0
0
7
0
0
6
Condition Code Register (CCR)
0
0
5
—
X
4
Access: Supervisor read/write
and
—
N
3
Freescale Semiconductor
Section 6.3.2,
—
Z
2
BDM read/write
—
V
1
—
C
0