MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 313
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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You control the FEC by writing into control registers located in each block. The CSR (control and status
registers) block provides global control (Ethernet reset and enable) and interrupt managing registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and
FEC_MDIO (management data input/output) lines of the MII interface.
The FEC DMA block (not to be confused with the device’s eDMA controller) provides multiple channels
allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run
independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC, but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3
counters. See
17.1.3
The FEC incorporates the following features:
Freescale Semiconductor
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Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
IEEE 802.3 full duplex flow control
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate
of 50 MHz
Retransmission from transmit FIFO following a collision (no processor bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
Features
Section 17.4.1, “MIB Block Counters Memory Map,”
for more information.
Fast Ethernet Controller (FEC)
17-3
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