MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet
MCF5282CVM66
Specifications of MCF5282CVM66
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MCF5282CVM66 Summary of contents
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MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual Devices Supported: MCF5214 MCF5216 MCF5280 MCF5281 MCF5282 Document Number: MCF5282UM Rev. 3 2/2009 ® ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc ...
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Enhanced Multiply-Accumulate Unit (EMAC) ColdFire Flash Module (CFM) System Control Module (SCM) Interrupt Controller Modules Edge Port Module (EPORT) External Interface Module (EIM) Synchronous DRAM Controller Module Fast Ethernet Controller (FEC) Programmable Interrupt Timer (PIT) Modules General Purpose Timer (GPT) ...
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Overview 1 ColdFire Core 2 Enhanced Multiply-Accumulate Unit (EMAC) 3 Cache 4 Static RAM (SRAM) 5 ColdFire Flash Module (CFM) 6 Power Management 7 System Control Module (SCM) 8 Clock Module 9 Interrupt Controller Modules 10 Edge Port Module (EPORT) ...
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... Supervisor/User Stack Pointers (A7 and OTHER_A7 2-5 2.2.4 Condition Code Register (CCR 2-6 2.2.5 Program Counter (PC 2-7 2.2.6 Cache Control Register (CACR 2-7 2.2.7 Access Control Registers (ACRn 2-7 2.2.8 Vector Base Register (VBR 2-7 Freescale Semiconductor Chapter 1 Overview Chapter 2 ColdFire Core v ...
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... Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 MAC Status Register (MACSR 3-3 3.2.2 Mask Register (MASK 3-5 3.2.3 Accumulator Registers (ACC0– 3-6 3.2.4 Accumulator Extension Registers (ACCext01, ACCext23 3-7 3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.1.1 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 vi Chapter 3 Freescale Semiconductor ...
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... CFM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.2 Flash Base Address Register (FLASHBAR 6-5 6.3.3 CFM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.4.1 CFM Configuration Register (CFMCR 6-8 6.3.4.2 CFM Clock Divider Register (CFMCLKD 6-9 Freescale Semiconductor Chapter 4 Cache Chapter 5 Static RAM (SRAM) Chapter 6 ...
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... Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.1 ColdFire Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.2 Static Random-Access Memory (SRAM 7-6 7.3.2.3 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.4 System Control Module (SCM 7-7 7.3.2.5 SDRAM Controller (SDRAMC 7-7 7.3.2.6 Chip Select Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 viii Chapter 7 Power Management Freescale Semiconductor ...
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... Bus Master Park Register (MPARK 8-9 8.6 System Access Control Unit (SACU 8-11 8.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3.1 Master Privilege Register (MPR 8-13 8.6.3.2 Peripheral Access Control Registers (PACR0–PACR8 8-13 Freescale Semiconductor Chapter 8 ix ...
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... Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.9 Loss of Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.10 Alternate Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.11 Loss of Clock in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 10.1 68K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 x Chapter 9 Clock Module Chapter 10 Interrupt Controller Modules Freescale Semiconductor ...
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... Chip Select Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4.1.1 Chip Select Address Registers (CSAR0–CSAR6 12-6 12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6 12-6 12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6 12-7 Freescale Semiconductor Chapter 11 Edge Port Module (EPORT) Chapter 12 Chip Select Module ...
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... SDRAM Column Address Strobe (SCAS 14-21 14.2.2.3 SDRAM Write Enable (DRAMW 14-21 14.2.2.4 SDRAM Bank Selects (SDRAM_CS[1:0 14-21 14.2.2.5 SDRAM Clock Enable (SCKE 14-22 14.2.3 Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.1 Reset In (RSTI 14-22 xii Chapter 13 Chapter 14 Signal Descriptions Freescale Semiconductor ...
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... Transmit Serial Data Output (UTXD[2:0 14-26 14.2.10.2 Receive Serial Data Input (URXD[2:0 14-26 14.2.10.3 Clear-to-Send (UCTS[1:0 14-26 14.2.10.4 Request-to-Send (URTS[1:0 14-27 14.2.11General Purpose Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11.1 GPTA[3: 14-27 14.2.11.2 GPTB[3: 14-27 14.2.11.3 External Clock Input (SYNCA/SYNCB 14-27 14.2.12DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 Freescale Semiconductor xiii ...
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... Power and Ground for Flash Array (VDDF, VSSF 14-32 14.2.16.7 Standby Power (VSTBY 14-32 14.2.16.8 Positive Supply (VDD 14-32 14.2.16.9 Ground (VSS 14-32 Synchronous DRAM Controller Module 15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 Block Diagram and Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 SDRAM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 xiv Chapter 15 Freescale Semiconductor ...
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... Dual-Address Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3 Channel Initialization and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.1 Channel Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.2 Programming the DMA Controller Module . . . . . . . . . . . . . . . . . . . 16-12 16.5.4 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.1 Auto-Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.2 Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.5 Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 Freescale Semiconductor Chapter 16 DMA Controller Module xv ...
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... Buffer Size Register (EMRBR 17-24 17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.5.1 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.5.1.1 Driver/DMA Operation with Buffer Descriptors . . . . . . . . . . . . . . . . 17-25 17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD 17-27 17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD 17-29 17.5.2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 xvi Chapter 17 Freescale Semiconductor ...
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... Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2.1 PIT Control and Status Register (PCSRn 19-3 19.2.2 PIT Modulus Register (PMRn 19-5 19.2.3 PIT Count Register (PCNTRn 19-5 19.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 Freescale Semiconductor Chapter 18 Watchdog Timer Module Chapter 19 xvii ...
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... Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.6.7 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.1 GPT Channel Interrupts (CnF 20-21 20.8.2 Pulse Accumulator Overflow (PAOVF 20-22 xviii Chapter 20 Freescale Semiconductor ...
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... QSPI Address Register (QAR 22-7 22.3.6 QSPI Data Register (QDR 22-8 22.3.7 Command RAM Registers (QCR0–QCR15 22-8 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.1 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.2 Transmit RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 Freescale Semiconductor Chapter 21 DMA Timers (DTIM0–DTIM3) Chapter 22 xix ...
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... Local Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.3.3 Remote Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.1 Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.2 Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 xx Chapter 23 UART Modules Freescale Semiconductor ...
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... External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.2 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3 Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1.1 Common Fields for Extended and Standard Format Frames . . . . . . 25-5 25.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 Freescale Semiconductor Chapter Interface Chapter 25 FlexCAN ...
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... Interrupt Mask Register (IMASK 25-27 25.5.10Interrupt Flag Register (IFLAG 25-28 25.5.11FlexCAN Receive Error Counter (RXECTR 25-29 25.5.12FlexCAN Transmit Error Counter (TXECTR 25-30 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 xxii Chapter 26 General Purpose I/O Module Freescale Semiconductor ...
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... Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.5.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.5.3.1 Chip Configuration Register (CCR 27-4 27.5.3.2 Reset Configuration Register (RCON 27-5 27.5.3.3 Chip Identification Register (CIR 27-6 27.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.2 Chip Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 Freescale Semiconductor Chapter 27 xxiii ...
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... QADC Status Register 1 (QASR1 28-23 28.6.7 Conversion Command Word Table (CCW 28-24 28.6.8 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.6.8.1 Right-Justified Unsigned Result Register (RJURR 28-27 28.6.8.2 Left-Justified Signed Result Register (LJSRR 28-27 28.6.8.3 Left-Justified Unsigned Result Register (LJURR 28-28 xxiv Chapter 28 Freescale Semiconductor ...
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... Analog Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-56 28.9.3 Conversion Timing Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-58 28.9.4 Analog Supply Filtering and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-61 28.9.5 Accommodating Positive/Negative Stress Conditions . . . . . . . . . . . . . . . . . 28-62 28.9.6 Analog Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-64 28.9.7 Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-66 28.9.7.1 Settling Time for the External Circuit . . . . . . . . . . . . . . . . . . . . . . . 28-67 Freescale Semiconductor xxv ...
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... Revision A Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.4.2 Address Attribute Trigger Register (AATR 30-7 30.4.3 Address Breakpoint Registers (ABLR, ABHR 30-9 30.4.4 Configuration/Status Register (CSR 30-10 30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR 30-12 xxvi Chapter 29 Reset Controller Module Chapter 30 Debug Support Freescale Semiconductor ...
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... Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.7 Processor Status, DDATA Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.7.1 User Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.7.2 Supervisor Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43 30.8 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-45 IEEE 1149.1 Test Access Port (JTAG) 31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31 ...
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... Async Inputs Signal Timing (ECRS and ECOL 33-23 33.13.4MII Serial Management Channel Timing (EMDIO and EMDC 33-23 33.14DMA Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.15QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.16JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-25 33.17Debug AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-27 xxviii Chapter 32 Mechanical Data Chapter 33 Electrical Characteristics Freescale Semiconductor ...
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... B.3 Changes Between Rev. 1 and Rev B-5 B.4 Changes Between Rev. 2 and Rev. 2 B-7 B.5 Changes Between Rev. 2.1 and Rev. 2 B-7 B.6 Changes Between Rev. 2.2 and Rev. 2 B-7 B.7 Changes Between Rev. 2.3 and Rev B-8 Freescale Semiconductor Appendix A Register Memory Map Appendix B Revision History ...
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... Freescale Semiconductor ...
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... Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson. • Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A . Patterson and John L. Hennessy. ColdFire Documentation ColdFire documentation is available from the sources listed on the back cover of this manual, as well as our web site, http://www.freescale.com/coldfire. Freescale Semiconductor xxxi ...
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... Application notes — These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of ColdFire documentation, refer to http://www.freescale.com/coldfire. ...
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... Fast Ethernet Controller (FEC) (not available on the MCF5214 and MCF5216) — 10BaseT capability, half- or full-duplex — 100BaseT capability, half- or limited-throughput full-duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller Freescale Semiconductor Figure 1-1. The main features are as follows: 1-1 ...
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... Media-independent interface (MII) to transceiver (PHY) • FlexCAN 2.0B Module — Includes all existing features of the Freescale TouCAN module — Full implementation of the CAN protocol specification version 2.0B – Standard data and remote frames (up to 109 bits long) – Extended data and remote frames (up to 127 bits long) – ...
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... DMA trigger capability on input capture or reference-compare • Two 4-channel general purpose timers — Four 16-bit input capture/output compare channels per timer — 16-bit architecture — Programmable prescaler — Pulse widths variable from microseconds to seconds — Single 16-bit pulse accumulator Freescale Semiconductor Overview 1-3 ...
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... SDRAM controller supports 8-, 16-, and 32-bit wide memory devices — Glueless interface to SRAM devices with or without byte strobe inputs — Programmable wait state generator — 32-bit bidirectional data bus — 24-bit address bus — seven chip selects available — Byte/write enables (byte strobes) 1-4 Freescale Semiconductor ...
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... Up to 142 bits of general purpose I/O for MCF5280/1/2 — 134 bits of general purpose I/O for MCF5214/6 — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system-level board testing Freescale Semiconductor Overview 1-5 ...
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... D-Cache/I-Cache DMA UART0 UART1 UART2 Timer Serial Serial Serial Modules I/O I/O I/O (DTIM0– DTIM3) General General Purpose Purpose QADC QSPI Timer A Timer B Test Controller 64K SRAM EMAC Watchdog Timer Module PIT Timers FlexCAN (PIT0– PIT3) Freescale Semiconductor ...
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... The memory is ideal for storing critical code or data structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. Freescale Semiconductor Table 1-1. Cache Configuration Tag Address Data Array Address ...
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... This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Freescale’s 683xx family of parts. The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register ...
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... Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level. Freescale Semiconductor Overview 1-9 ...
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... Automatic wake-up mode for multidrop applications • Four maskable interrupt conditions • All three UARTs have DMA request capability • Parity, framing, and overrun error detection • False-start bit detection • Line-break detection and generation 1-10 Freescale Semiconductor ...
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... VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. 1.1.16 DMA Controller The Direct Memory Access (DMA) controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels (DMA0–DMA3) that allow Freescale Semiconductor Overview 1-11 ...
Page 44
... FlexCAN contains 16 message buffers. 2 1.2 Bus The bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. 1-12 NOTE Freescale Semiconductor ...
Page 45
... The digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. Also included are the periodic/interval timer, control and status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table. Freescale Semiconductor Overview 1-13 ...
Page 46
... Overview 1-14 Freescale Semiconductor ...
Page 47
... DSOC Operand Execution Pipeline AGEX The instruction fetch pipeline (IFP two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the Freescale Semiconductor Instruction Address Generation Instruction Fetch Cycle FIFO Instruction Buffer Decode & ...
Page 48
... Four 32-bit accumulators (ACC0–ACC3) – Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23). 2-2 Table 2-1 lists the processor registers. Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC : Freescale Semiconductor ...
Page 49
... MAC Accumulators 0–3 (ACC0–3) 0x80A, 0x80B 0x807 MAC Accumulator 0,1 Extension Bytes (ACCext01) 0x808 MAC Accumulator 2,3 Extension Bytes (ACCext23) 0x80E Condition Code Register (CCR) Freescale Semiconductor Width Access Reset Value (bits) Supervisor/User Access Registers 32 R/W 0xCF20_6080 32 R/W ...
Page 50
... Written with Reset Value Section/Page MOVEC Contents of No 2.2.5/2-7 location 0x0000_0004 0x0000_0000 Yes 2.2.6/2-7 See Section Yes 2.2.7/2-7 Contents of No 2.2.3/2-5 location 0x0000_0000 0x0000_0000 Yes 2.2.8/2-7 0x27-- No 2.2.9/2-8 0x0000_0000 Yes 2.2.10/2-8 See Section Yes 2.2.10/2-8 Access: User read/write BDM read/write Freescale Semiconductor ...
Page 51
... These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other instruction references to the stack pointer, explicit or implicit, access the active A7 register. The SSP is loaded during reset exception processing with the contents of location 0x0000_0000. Freescale Semiconductor Address Figure 2-3. Address Registers (A0–A6) NOTE ...
Page 52
... Carry condition code bit. Set if a carry out of the operand msb occurs for an addition borrow occurs subtraction; otherwise cleared. 2-6 OTHER_A7: Supervisor or BDM read/write Address — — Table 2-2. CCR Field Descriptions Description Access: A7: User or BDM read/write Access: User read/write BDM read/write — — — Freescale Semiconductor ...
Page 53
... ColdFire processors. They are assumed to be zero, forcing the table to be aligned boundary. BDM: 0x801 (VBR Base Address W Reset Freescale Semiconductor Address Section 4.2.1, “Cache Control Register (CACR).” Figure 2-7. Vector Base Register (VBR) ColdFire Core Access: User read/write BDM read/write ...
Page 54
... Section 5.3.1, “SRAM Base Address Register (RAMBAR)” “Flash Base Address Register (FLASHBAR)”. 2 Figure 2-8. Status Register (SR) Table 2-3. SR Field Descriptions Description (CCR)”. Access: Supervisor read/write BDM read/write Condition Code Register (CCR — — — — — and Section 6.3.2, Freescale Semiconductor ...
Page 55
... Figure 2-10 below. In these diagrams, the internal structure of the instruction fetch and operand execution pipelines is shown: IAG +4 Figure 2-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram Freescale Semiconductor 2-1, the non-Harvard architecture of the processor is readily apparent. IC Core Bus Address FIFO Core Bus ...
Page 56
... Ry,<mem>x For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and fetching of the required register operands (OC) from the dual-ported register file, while the actual 2-10 DSOC AGEX Core Bus Address Core Bus Write Data Freescale Semiconductor ...
Page 57
... RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load instruction ( ) is optimized to support a two-cycle execution time. The following example move.l <mem>y,Rx in Figure 2-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement added to a base register Ay. Freescale Semiconductor Operand Execution Pipeline DSOC AGEX Rx Ry ColdFire Core Figure 2-11 ...
Page 58
... Ax. 2-12 Operand Execution Pipeline DSOC AGEX Ay Operand Execution Pipeline DSOC AGEX Rx <mem>y Figure 2-14 where the effective address is of the form <ea>y Core Bus Address Core Bus Write Data new Rx Core Bus Address Core Bus Write Data Freescale Semiconductor ...
Page 59
... Core Bus Read Data Figure 2-14. V2 OEP Register-to-Memory The pipeline timing diagrams of instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown progressing down the operand execution pipeline. Freescale Semiconductor Operand Execution Pipeline DSOC AGEX Ax Figure 2-15 ...
Page 60
... ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three areas: 1. Enhanced support for byte and word-sized operands 2. Enhanced support for position-independent code 3. Miscellaneous instruction additions to address new functionality 2-14 next read next AGEX op write next EX Freescale Semiconductor ...
Page 61
... For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to special locations within the interrupt controller’s address space with the interrupt level encoded in the address. Freescale Semiconductor Description Section 2.3.4.1, ColdFire Core ...
Page 62
... Next 0x034 — 0x038 Fault — 0x060 Next — 2-16, the processor uses a simplified for details on Assignment Access error Address error Illegal instruction Divide by zero Reserved Privilege violation Trace Debug interrupt Reserved Format error Reserved Spurious interrupt Reserved Freescale Semiconductor ...
Page 63
... There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other exceptions. See Freescale Semiconductor Stacked Vector Program Offset (Hex) Counter Next Trap # 0-15 instructions — ...
Page 64
... The NOP instruction can collect access errors for writes. This instruction delays its 2-18 Table 2-7. Fault Status Encodings Definition Reserved Error on instruction fetch Reserved Reserved Error on operand write Attempted write to write-protected space Reserved Error on operand read Reserved Reserved Freescale Semiconductor ...
Page 65
... PC-relative change-of-flow instructions Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR) 0x7 Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ) 0x8 Logical OR (OR) 0x9 Subtract (SUB), Subtract Extended (SUBX) Freescale Semiconductor Figure OpMode Instruction Class ColdFire Core 2-17 ...
Page 66
... The instruction before the stop executes and then generates a trace exception. In the exception stack frame, the PC points to the stop opcode. 2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate operand from the instruction. 2-20 Instruction Class Freescale Semiconductor ...
Page 67
... Freescale Semiconductor for a detailed explanation of this exception, which is generated in ColdFire Core ...
Page 68
... After the initial instruction is fetched from memory, program execution begins at the address in the PC access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault state. 2-22 for details. ,” for details on the interrupt controller. NOTE Freescale Semiconductor ...
Page 69
... EMAC execute engine is present in core. (This is the value used for this device.) 12 FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core. FPU 0 FPU execute engine not present in core. (This is the value used for this device.) 1 FPU execute engine is present in core. Freescale Semiconductor ...
Page 70
... Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. CLSZ 29–28 Configurable cache associativity. CCAS 00 Four-way 01 Direct mapped (This is the value used for this device) Else Reserved for future use 2-24 Description CCSZ FLASHSZ Description Access: User read-only BDM read-only SRAMSZ Freescale Semiconductor ...
Page 71
... Each timing entry is presented as C(R/W) where: • the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. Freescale Semiconductor Description ColdFire Core 2-25 ...
Page 72
... PC-relative effective addressing modes is the same for the comparable An-relative mode. 2-26 Bus Additional Size Operations C(R/W) Word Byte, Byte 2(1/0) if read 1(0/1) if write Long Byte, Word, 3(2/0) if read Byte 2(0/2) if write Long Word, Word 2(1/0) if read 1(0/1) if write Table 2-13 lists timings for MOVE.L. NOTE Freescale Semiconductor ...
Page 73
... Freescale Semiconductor equals ET with {<ea> = (d16,An)} equals ET with {<ea> = (d8,An,Xi*SF)} Destination (Ax) (Ax)+ -(Ax) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) ...
Page 74
... Freescale Semiconductor ...
Page 75
... REMU.L <ea>,Dx SUB.L <ea>,Rx 1(0/0) SUB.L Dy,<ea> — SUBI.L #imm,Dx 1(0/0) SUBQ.L #imm,<ea> 1(0/0) SUBX.L Dy,Dx 1(0/0) Freescale Semiconductor Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) — — — — — — — — 4(1/1) 4(1/1) 4(1/1) ...
Page 76
... Freescale Semiconductor 2 3 ...
Page 77
... Dx MULS.W <ea>y, Dx MULU.L <ea>y, Dx MULU.W <ea> Effective address of (d16,PC) not supported 2 Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] equals 1---, -11-, --11) Freescale Semiconductor Effective Address Rn (An) (An)+ -(An) (d16,An) 1(0/0) — — — — ...
Page 78
... Forward Backward Taken Not Taken Taken 3(0/0) 1(0/0) 2(0/0) (d8,An,Xi*SF) xxx.wl #xxx (d8,PC,Xi*SF) — — — — — — 4(0/0) 3(0/0) — 4(0/1) 3(0/1) — — — — — — — Backward Not Taken 3(0/0) Freescale Semiconductor ...
Page 79
... A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the dynamic number range when implementing signal processing algorithms The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module Freescale Semiconductor (Figure 3-1). 3-1 ...
Page 80
... Operand Y Operand X X Shift 0,1,- Accumulator( – – ∑ ∑ – + – Equation 3 simple, four-tap FIR filter, shown – + Equation 3-1. Eqn. 3 Eqn. 3-2 – + – Freescale Semiconductor ...
Page 81
... MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR instruction or the accumulator is loaded directly. Bit 11: Accumulator 3 ... Bit 8: Accumulator 0 Freescale Semiconductor Table 3-1. EMAC Memory Map Width Register (bits) 32 ...
Page 82
... Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load Z operations not affected by MULS and MULU instructions. 3-4 Description Section 3.3.1.1, “Rounding”. The resulting 16-bit value is stored in the -31 for 32-bit fractions. See Section 3.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is Section 3.3.4, “Data Freescale Semiconductor ...
Page 83
... This minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows: mac.sz Ry,RxSF,<ea>yand ,Rw Freescale Semiconductor Description R/T Operational Modes x ...
Page 84
... The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers form the entire 48-bit result. 3-6 {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF, MASK} {0xFFFF0x, MASK} Figure 3-3. Mask Register (MASK) Table 3-4. MASK Field Descriptions Description Access: User read/write BDM read/write MASK Freescale Semiconductor ...
Page 85
... Accumulator 0 lower extension byte ACC0L 15–8 Accumulator 1 upper extension byte ACC1U 7–0 Accumulator 1 lower extension byte ACC1L Freescale Semiconductor Accumulator Table 3-5. ACC0–3 Field Descriptions Description ACC0L ACC1U Table 3-6. ACCext01 Field Descriptions Description Enhanced Multiply-Accumulate Unit (EMAC) Access: User read/write ...
Page 86
... For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. 3-8 ACC2L ACC3U Table 3-7. ACCext23 Field Descriptions Description Access: User read/write BDM read/write ACC3L Freescale Semiconductor ...
Page 87
... Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} if MACSR[6: signed fractional mode */ Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6: unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects the register. Freescale Semiconductor OperandY 32 OperandX ...
Page 88
... Let the high-order 16 bits named R0.U and the low-order 16 bits be R0.L. • If R0.L is less than 0x8000, the result is truncated to the value of R0.U. • If R0.L is greater than 0x8000, the upper word is incremented (rounded up). 3-10 ). The lsbs of the 48-bit accumulator move.l ACCx,Rx Freescale Semiconductor ...
Page 89
... This code performs the EMAC state restore: EMAC_state_restore: Freescale Semiconductor Enhanced Multiply-Accumulate Unit (EMAC) /* R0.L = 0x8000 */ ; save the macsr ; zero the register to ... ; disable rounding in the macsr ; save the accumulators ; save the accumulator extensions ; save the address mask ...
Page 90
... Writes the contents of an accumulator to a CPU register Copies a 48-bit accumulator Writes a value to MACSR Write the contents of MACSR to a CPU register Write the contents of MACSR to the CCR Writes a value to the MASK register Writes the contents of the MASK to a CPU register operand Description Freescale Semiconductor ...
Page 91
... The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the recently updated accumulator 0 value is available. Freescale Semiconductor Enhanced Multiply-Accumulate Unit (EMAC) Description ...
Page 92
... For the EMAC, assemblers support this syntax and no explicit reference to an accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the destination accumulator is explicitly defined. 3-14 Equation 3- – ∑ ⋅ ) – – ⋅ = – – (N-1) -31 ). (MACSR)”. (N- The a a ... N-1 N-2 N Eqn. 3-3 . -15 ); Freescale Semiconductor ...
Page 93
... MACSR.PAVn = 1 MACSR (inst == MSAC and and then if (product[63 else if (MACSR.OMC == 1) } Freescale Semiconductor (product[63:39] != 0xffff_ff_1)) /* product overflow */ MACSR.OMC == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 then /* overflowed MAC, saturationMode enabled */ if (product[63 then result[47:0] = 0xffff_8000_0000 ...
Page 94
... MACSR.PAVn = 0 if (sz == word) then {if (U/ then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], if (U/ 3-16 /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ saturationMode enabled */ if (result[47 then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 /* sign-extend */ 0x0000} Freescale Semiconductor ...
Page 95
... MACSR.PAVn == 0) then { MACSR.PAVn = 0 /* select the input operands */ if (sz == word) then {if (U/ then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/ Freescale Semiconductor 0x0000} then product[63:24] = product[63:24 (operandX[31:0] == 0x8000_0000)) /* zero-fill */ /* sign-extend */ saturationMode enabled */ if (result[47 then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000 ...
Page 96
... MSAC and and then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) 3-18 /* product overflow */ MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff /* zero-fill upper byte */ /* 2-bit scale factor */ /* no scaling specified */ /* SF = “<< 1” reserved encoding */ /* SF = “>> 1” */ MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ Freescale Semiconductor ...
Page 97
... ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVn MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR else MACSR (ACCx[47:32] == 0x0000) then MACSR. else MACSR. break; } Freescale Semiconductor Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff 3-19 ...
Page 98
... Enhanced Multiply-Accumulate Unit (EMAC) 3-20 Freescale Semiconductor ...
Page 99
... This address field is compared to bits [31: or data-only configurations and to bits [31: bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the Freescale Semiconductor 128 -entry tag array (containing addresses and × ...
Page 100
... Three supervisor registers define the operation of the cache and local bus controller: the cache control register (CACR) and two access control registers (ACR0, ACR1). 4 Line Buffer Address = Fill Hit TAG 127 = Tag Hit Table 4-1 External Data[31: Line Buffer Storage MUX DATA 511 MUX Local Data Bus below shows the memory map Freescale Semiconductor ...
Page 101
... CENB (disable instruction caching) and DISD (disable data caching) bits, control the cache configuration. 0 Cache disabled 1 Cache enabled Table 4-3 describes cache configuration. 30–29 Reserved, must be cleared. Freescale Semiconductor Table 4-1. Cache Memory Map Width (bits Figure 4-2, is shown as read/write. At system reset, the ...
Page 102
... CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into the memory array. See Table 0 Disable burst fetches on non-cacheable accesses 1 Enable burst fetches on non-cacheable accesses 4-4 Description Table 4-4 describes how to set the cache invalidate all bit. Table 4-4 describes how to set the cache invalidate all bit. 4-7. Freescale Semiconductor ...
Page 103
... Table 4-4 shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache invalidate all bit (CACR[CINV]). Freescale Semiconductor Description Attributes. Section 2.2.3, “Supervisor/User Stack Pointers (A7 and Table 4-6 for external fetch size based on miss address and CLNF. ...
Page 104
... Invalidate only 1 KByte instruction cache Data Cache 1 Split Instruction/ No invalidate Data Cache x Instruction Cache Invalidate 2 KByte instruction cache x Data Cache Invalidate 2 KByte data cache Figure NOTE – – Operation 4-3, is shown as read/write. At Access: Supervisor write-only BDM read/write BWE – – – Freescale Semiconductor ...
Page 105
... The cache processes any fetch access in the normal manner. 4.3.1 Interaction with Other Modules Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing. Freescale Semiconductor Table 4-5. ACRn Field Descriptions Description Cache 4-7 ...
Page 106
... A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the cache can be enabled. 4-8 :4] of the source address register is invalidated, provided CACR[CPDI] 10 that selects Freescale Semiconductor ...
Page 107
... Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated. Freescale Semiconductor Table 4-6 shows the relationship between the CLNF bits, ...
Page 108
... All instruction fetches are word or longword in size, and not loaded into the line-fill buffer Instruction fetch size is defined by loaded into the line-fill buffer, but are never written into the memory array. Table 4-6 and contents of the Table 4-6 and Freescale Semiconductor ...
Page 109
... All undefined bits in the register are reserved. These bits are ignored during writes to the RAMBAR, and return zeroes when read from the debug module. • The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected. Freescale Semiconductor (SCM)” for more information. 5-1 ...
Page 110
... DMA or CPU has priority in lower 32k bank of memory. If bit is set, CPU has priority. If bit is cleared, DMA has priority. Priority is determined according to the following table. NOTE: The Freescale-recommended setting for the priority bits is 00. 9 SPV Secondary port valid. Allows access by DMA 0 DMA access to memory is disabled ...
Page 111
... SRAM at 0x20000000 and then initializes the SRAM to zeros. RAMBASE EQU $20000000 RAMVALID EQU $00000001 move.l #RAMBASE+RAMVALID,D0 movec.l D0, RAMBAR Freescale Semiconductor Description Section 5.3.4, “Power ;set this variable to $20000000 ;load RAMBASE + valid bit into D0. ;load RAMBAR and enable SRAM Static RAM (SRAM) 5-3 ...
Page 112
... Table 5-2. Typical RAMBAR Setting Examples Data Contained in SRAM Both Code And Data 5-4 ;load pointer to SRAM ;load loop counter into D0 ;clear 4 bytes of SRAM ;decrement loop counter ;if done, then exit; else continue looping RAMBAR[7:0] Code Only 0x2B Data Only 0x35 0x21 Freescale Semiconductor ...
Page 113
... Auto-sense amplifier timeout for low-power, low-frequency read operations Enabling Flash security will disable BDM communications. When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration. Freescale Semiconductor NOTE ) used for all module operations DD NOTE NOTE ...
Page 114
... An erased Flash bit reads 1 and a programmed Flash bit reads 0. The CFM features a sense amplifier timeout (SATO) block that automatically reduces current consumption during reads at low system clock frequencies. 6-2 contains the Flash physical blocks, the ColdFire Flash bus and IP Freescale Semiconductor ...
Page 115
... Flash Control Registers Note: Mass Erase Block 0 (256 Kbytes) = Flash Physical Block 0 and Flash Physical Block 1. Mass Erase Block 1 (256 Kbytes) = Flash Physical Block 2 and Flash Physical Block 3 (MCF5282 and MCF5216 only) Freescale Semiconductor Internal Bus Flash Physical Block 3 Memory Array ...
Page 116
... Figure 6-2. CFM Array Memory Map (CFMPROT)”). A similar mechanism is available to control Flash Physical Block 3 3H[31] 3L[31] Memory Memory Array 3H Array 3L 3H[0] 3L[0] Flash Physical Block 1 1H[31] 1L[31] Memory Memory Array 1H Array 1L 1H[0] 1L[0] (16 bits wide × 32K) (32 bits wide × 32K) Freescale Semiconductor ...
Page 117
... FLASHBAR located in the processor’s CPU space will be invalid and it must be initialized with the valid bit set before the CPU (or modules) can access the on-chip Flash. Freescale Semiconductor Table 6-1 describes each byte used in this field. Table 6-1. CFM Configuration Field ...
Page 118
... Note: The reset value for the valid bit is determined by the chip mode selected at reset (see “Chip Configuration Module Figure 6-3. Flash Base Address Register (FLASHBAR) 6-6 NOTE NOTE (CCM)” for more details. When the default reset 0000_0000_0000_0000 R — C/I 0000_0001_0010_000 R CPU + 0xC04 (CCM)”). Chapter 27, “Chip — See Note R/W Chapter 27, Freescale Semiconductor ...
Page 119
... Bits 31–24 0x1D_0000 0x1D_0004 0x1D_0008 0x1D_000C 0x1D_0010 Freescale Semiconductor Description Base address field. Defines the 0-modulo-512K base address of the Flash module. By programming this field, the Flash may be located on any 512Kbyte boundary within the processor’s four gigabyte address space. Reserved, should be cleared. ...
Page 120
... PVIOL interrupts disabled. Access error interrupt enable. The AEIE bit is readable and writable. The AEIE bit enables an interrupt in case the access error flag, ACCERR, is set interrupt will be requested whenever the ACCERR flag is set. 0 ACCERR interrupts disabled. 1 Bits 7–0 Access — Freescale Semiconductor ...
Page 121
... Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the CFM input clock down to a frequency between 150 kHz and 200 kHz. The frequency range of the CFM clock is 150 kHz to 102.4 MHz. Freescale Semiconductor Table 6-4. CFMCR Field Descriptions Description Command buffer empty interrupt enable ...
Page 122
... Back door to Flash is enabled. 0 Back door to Flash is disabled. 30 SECSTAT Flash security status 1 Flash security is enabled 0 Flash security is disabled 6-10 NOTE Section 6.4.3.1, “Setting the CFMCLKD NOTE NOTE — See Note R SEC See Note R IPSBAR + 0x1D_0008 Table 6-6. CFMSEC Field Descriptions Description 16 0 Freescale Semiconductor ...
Page 123
... Reserved. Should be cleared. 15–0 SEC[15:0] Security field. The SEC bits define the security state of the device; see below. The security features of the CFM are described in Freescale Semiconductor Table 6-6. CFMSEC Field Descriptions Description SEC[15:0] 0x4AC8 All other combinations 1 The 0x4AC8 value was chosen because it represents the ColdFire Halt ...
Page 124
... CFMPROT and its corresponding logical sector. Since the MCF5281 and MCF5214 devices contain a 256-Kbyte Flash, only CFMPROT[15:0] is used. 6-12 PROT See Note R/W PROT See Note R/W IPSBAR + 0x1D_0010 Table 6-7. CFMPROT Field Descriptions Description NOTE 16 0 Freescale Semiconductor ...
Page 125
... Field Reset R/W Address Note: The CFMPROT register is loaded at reset from the Flash Supervisor/user Space Restrictions longword stored at the array base address + 0x0000_040C. Figure 6-9. CFM Supervisor Access Register (CFMSACC) Freescale Semiconductor SECTOR 31 • • • } SECTOR 2 Protected Flash Logical Sectors ...
Page 126
... Logical sector is mapped in data address space. 0 Logical sector is mapped in data and program address space 6-14 Table 6-8. CFMSACC Field Descriptions Description for details. DATA See Note R/W DATA See Note R/W IPSBAR + 0x1D_0018 Table 6-9. CFMDACC Field Descriptions Description 16 0 Figure 6-8 for . Freescale Semiconductor ...
Page 127
... ACCERR is cleared by writing Writing ACCERR has no effect. While ACCERR is set in this register not possible to launch another command. See User Mode Illegal 1 Access error has occurred 0 3 — Reserved, should be cleared. Freescale Semiconductor 6 5 CCIF PVIOL ACCERR — BLANK 1100_0000 R ...
Page 128
... CMD 0000_0000 R/W IPSBAR + 0x1D_0024 Table 6-11. CFMCMD Field Descriptions Description Name RDARY1 PGM PGERS MASERS PGERSVER 0 Table 6-12. Writing a Table 6-12 will set the ACCERR Description Erase verify (all 1s) Longword program Page erase Mass erase Page erase verify Freescale Semiconductor ...
Page 129
... MHz, PRDIV8 = 1; otherwise PRDIV8 = SYS 2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result and discard any fraction. Do not round the result. 3. Thus the Flash state machine clock will be: Freescale Semiconductor f SYS DIV[5: 200kHz (PRDIV8 x 7)) ColdFire Flash Module (CFM) ...
Page 130
... MHz: SYS f SYS 2 x 200kHz (PRDIV8 x 7)) 66 MHz = 400 kHz 7)) f SYS = 2 x (DIV[5: (PRDIV8 x 7)) 66 MHz = 7)) to 196.43 kHz which is a valid frequency CLK WARNING NOTE Operations”). = 20 = 196.43 kHz between CLK CLK . CLK Freescale Semiconductor ...
Page 131
... Page erase 0x41 Mass erase 0x06 Page erase verify Freescale Semiconductor NOTE Commands.” NOTE Figure 6-13. The flow is similar for the erase and Table 6-13. Flash User Commands Description Verify that all 256 Kbytes of Flash from two interleaving physical blocks are erased ...
Page 132
... NOTE: COMMAND SEQUENCE ABORTED BY WRITING 0x00 CBEIF BIT TO CFMUSTAT READ CFMUSTAT YES PVIOL WRITE 0x20 TO CLEAR SET? CFMUSTAT PVIOL BIT NO YES ACCERR WRITE 0x10 TO CLEAR SET? CFMUSTAT ACCERR BIT NO YES CBEIF SET? NO READ CFMUSTAT CCIF NO SET? YES EXIT YES NEXT WRITE? NO Freescale Semiconductor ...
Page 133
... MCU enters stop mode with a command in progress. Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. Freescale Semiconductor (CFMPROT)”). NOTE WARNING ColdFire Flash Module (CFM) ...
Page 134
... The CFM may be unsecured via one of two methods: 1. Executing a back door access scheme. 2. Passing an erase verify check. 6-22 NOTE NOTE Freescale Semiconductor ...
Page 135
... The CFM module can request an interrupt when all commands are completed or when the address, data, and command buffers are empty. Interrupt Source Command, data and address buffers empty Freescale Semiconductor NOTE Table 6-14 shows the CFM interrupt mechanism. Table 6-14. CFM Interrupt Sources ...
Page 136
... ColdFire Flash Module (CFM) Table 6-14. CFM Interrupt Sources (continued) Interrupt Source All commands are completed Access error 6-24 Interrupt Flag Local Enable CCIF CCIE (CFMUSTAT) (CFMCR) ACCERR AEIE (CFMUSTAT) (CFMCR) Freescale Semiconductor ...
Page 137
... This subsection provides a description of the memory map and registers. 7.2.1 Programming Model The PMM programming model consists of one register: • The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode. Freescale Semiconductor 7-1 ...
Page 138
... LPICR[XLPM_IPL[2:0]]. 7-2 Bits 23–16 Bits 15–8 Core Watchdog Low-Power 2 Control Register Interrupt Control (CWCR) Register (LPICR) 3 Reserved NOTE 1 Bits 7–0 Access Core Watchdog S Service Register (CWSR) Low-Power Control S Register (LPCR) Freescale Semiconductor ...
Page 139
... Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to 3–0 — Reserved, should be cleared. XLPM_IPL[2:0] 000 001 010 011 100 101 11x Freescale Semiconductor NOTE XLPM_IPL 0 1/0 0 R/W IPSBAR + 0x012 Table 7-2. LPICR Field Descriptions Description Table 7-3 ...
Page 140
... RCR[LVDE] bit is a logic 0. 1 VREG Pseudo-Standby mode (LVD enabled on power down request). 0 VREG Standby mode (LVD disabled on power down request). Reserved, should be cleared. Table 7-5. Low-Power Modes LPMD[1:0] Mode 11 STOP 10 WAIT 01 DOZE 00 RUN — LVDSE — Table 7-5 illustrates Freescale Semiconductor ...
Page 141
... An interrupt request which has been enabled at the module of the interrupt’s origin 7.3.1.1 Run Mode Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency. Freescale Semiconductor Operation During Stop Mode CLKOUT PLL Enabled ...
Page 142
... The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 7.3.2.2 Static Random-Access Memory (SRAM) SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode. 7-6 NOTE (SDRAMC)” for more Freescale Semiconductor ...
Page 143
... DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR becomes set. The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode. Freescale Semiconductor Modes” for the core Watchdog interrupt to bring the part out of NOTE ...
Page 144
... DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. 7-8 Freescale Semiconductor ...
Page 145
... When the CPU is inactive, a software reset cannot be generated to exit any low-power mode. 7.3.2.16 Chip Configuration Module The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so. Freescale Semiconductor Power Management 7-9 ...
Page 146
... In stop mode (or in doze mode programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value the responsibility of software to avoid erroneous operation. When not stopped, the PIT may generate an interrupt to exit the low-power modes. 7-10 Freescale Semiconductor ...
Page 147
... FlexCAN loses synchronization with the CAN bus, and STOP_ACK and NOT_RDY bits in MCR register are set. Exiting stop mode is done in one of the following ways: • Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR). • Clearing the STOP bit in the MCR. Freescale Semiconductor Power Management 7-11 ...
Page 148
... FlexCAN resumes its clocks. It then continues to monitor the conditions and stops/resumes its clocks appropriately. The following are conditions for the automatic shut-off of FlexCAN clocks: • No Rx/Tx frame in progress. • No moving of Rx/Tx frames between SMB and MB and no Tx frame is pending for transmission in any MB. 7-12 Freescale Semiconductor ...
Page 149
... STOP instruction is executed and the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode. Freescale Semiconductor NOTE Power Management 7-13 ...
Page 150
... Yes Enabled Yes 2 Yes Stopped No No Enabled Yes Enabled Yes No Stopped No No Stopped Yes Program Yes 2 2 Yes Stopped Yes 3 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped No 2 Yes Stopped Yes Enabled Yes No Enabled No Freescale Semiconductor ...
Page 151
... The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. Freescale Semiconductor Power Management 7-15 ...
Page 152
... Power Management 7-16 Freescale Semiconductor ...
Page 153
... Core watchdog service register (CWSR) to service watchdog timer • System bus master arbitration programming model (MPARK) • System access control unit (SACU) programming model — Master privilege register (MPR) — Peripheral access control registers (PACRs) — Grouped peripheral access control registers (GPACR0, GPACR1) Freescale Semiconductor 8-1 ...
Page 154
... RAMBAR — CWCR LPICR — MPARK MPR — PACR1 PACR2 — PACR5 — PACR8 GPACR1 — — — — — — — — — — Chapter 7, “Power Management." NOTE [7:0] 1 CWSR PACR3 PACR6 — — — — — Freescale Semiconductor ...
Page 155
... MOVEC instruction at CPU space address 0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR. Freescale Semiconductor NOTE — ...
Page 156
... For details on the processor's view of the local SRAM memories, see Register (RAMBAR).” 8 0000_0000_0000_0000 R BDE 0000_0000_0000_0000 R/W IPSBAR + 0x008 Table 8-3. RAMBAR Field Description Description Section 5.3.1, “SRAM Base Address Register NOTE (SRAM)” for more information — (RAMBAR).” Figure 8-2. Section 5.3.1, “SRAM Base Address Freescale Semiconductor ...
Page 157
... TA was asserted. The core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous ColdFire devices. However, there is a second watchdog timer available that has new features. See “Watchdog Timer Freescale Semiconductor NOTE Module”) provides indication of all reset — ...
Page 158
... If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 8 (ICR8) of INTC0. 1 Reserved; do not use. 8 CWT[2:0] CWTA 0000_0000 R/W IPSBAR + 0x011 Table 8-5. CWCR Field Description Description 1 0 CWTAVAL CWTIC Freescale Semiconductor ...
Page 159
... Internal Bus Arbitration The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which four MBus masters (M0–M3 in The function of the arbitration logic is described in this section. Freescale Semiconductor CWT Time-Out Period CWT 9 2 Bus clock frequency ...
Page 160
... The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin if any requester has been held for longer than a specified cycle count. 8-8 “back door” to SRAM and Flash MPARK RAMBAR EIM MARB Internal Modules SDRAMC Figure 8-6. Arbiter Module Functions Freescale Semiconductor ...
Page 161
... Master 3 (M3): Fast Ethernet Controller (Not used for the MCF5216 and MCF5214) • Master 2 (M2): 4-channel DMA • Master 1 (M1): Internal Bus Master (not used in normal user operation) • Master 0 (M0): V2 ColdFire Core Freescale Semiconductor System Control Module (SCM) 8-9 ...
Page 162
... Master priority level for master 1 (Not used in user mode) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 15 — Reserved, should be cleared. 8- M2_P_EN BCR24BIT M3_PRTY M2_PRTY M0_PRTY M1_PRTY 0011_0000_1110_0001 R LCKOUT_TIME 0000_0000_0000_0000 R/W IPSBAR + 0x01C Table 8-6. MPARK Field Description Description — Freescale Semiconductor 16 0 ...
Page 163
... If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module not accessed. Freescale Semiconductor System Control Module (SCM) Description ...
Page 164
... Reset state provides supervisor-only read/write access to each of these peripheral spaces 8.6.3 Memory Map/Register Definition The memory map for the SACU program-visible registers within the System Control Module (SCM) is shown in Figure 8-7. The MPR, PACR, and GPACRs are 8 bits in width. 8-12 Freescale Semiconductor ...
Page 165
... Peripheral Access Control Registers (PACR0–PACR8) Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single PACR defines the access level for each of the two modules. These modules only support operand reads Freescale Semiconductor Table 8-7. SACU Register Memory Map [23:20] ...
Page 166
... Table Supervisor Mode User Mode Read/Write No Access Read No Access Read Read Read No Access Read/Write Read/Write Read/Write Read Read/Write Read/Write No Access No Access Modules Controlled Name ACCESS_CTRL1 PACR0 SCM PACR1 EIM PACR2 UART0 2 0 ACCESS_CTRL0 8-10. 8-10. ACCESS_CTRL0 SDRAMC DMA UART1 Freescale Semiconductor ...
Page 167
... PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access control is not affected by GPACR0, even though the modules are mapped in its 64-Mbyte address space. 7 Field LOCK Reset Read/Write R/W Address Figure 8-10. Grouped Peripheral Access Control Register (GPACR) Freescale Semiconductor Modules Controlled Name ACCESS_CTRL1 PACR3 UART2 2 PACR4 I C — ...
Page 168
... Table 8-12. GPACR Field Descriptions Description Table 8-13. Supervisor Mode No Access No Access Read No Access Read / Write Read Read / Write No Access No Access No Access Read / Execute No Access Read / Write / Execute Read / Execute Read Execute Table 8-13. Table 8-14 shows the User Mode Freescale Semiconductor ...
Page 169
... Offset) GPACR0 0x0000_0000– 0x03FF_FFFF GPACR1 0x0400_0000– 0x07FF_FFFF Freescale Semiconductor Table 8-14. GPACR Address Space Modules Protected Ports, CCM, PMM, Reset controller, Clock, EPORT, WDOG, PIT0–PIT3, QADC, GPTA, GPTB, FlexCAN, CFM (Control) CFM (Flash module’s backdoor access for ...
Page 170
... System Control Module (SCM) 8-18 Freescale Semiconductor ...
Page 171
... In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency. The post divider is not active. 9.2.3 External Clock Mode In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency. Freescale Semiconductor 9-1 ...
Page 172
... Exit not caused by clock module, but normal clocking resumes upon mode exit Exit not caused by clock module, but clock sources are re-enabled and normal clocking Normal Table 9-1 shows the clock module Mode Exit resumes upon mode exit Exit not caused by clock module Freescale Semiconductor ...
Page 173
... EXTAL XTAL EXTERNAL CLOCK OSC STPMD[1:0] STOP MODE Figure 9-1. Clock Module Block Diagram Freescale Semiconductor CLKMOD[1:0] RSTOUT MFD PLLMODE REFERENCE CLOCK PLL PLLREF LOCEN LOLRE PLL CLOCK OUT CLKGEN PLLSEL DISCLK PLLMODE Clock Module CLKOUT LOCKS LOCK LOCS RFD[2:0] TO RESET ...
Page 174
... For more detailed Descriptions.” Table 9-2. Signal Properties Function Oscillator or clock input Oscillator output System clock output Clock mode select inputs Reset signal from reset controller LOCKS LOCK TO RESET MODULE LOCS VCO RFD[2:0] SCALED PLL CLOCK OUT PLL CLOCK OUT Freescale Semiconductor ...
Page 175
... Synthesizer status register (SYNSR), which reflects clock status 9.6.1 Module Memory Map IPSBAR Offset 0x0012_0000 0x0012_0002 CPU supervisor mode access only. Freescale Semiconductor Table 9-3. Clock Module Memory Map Register Name Synthesizer Control Register (SYNCR) Synthesizer Status Register (SYNSR) Clock Module Section 29.4.1, “Reset Control 1 ...
Page 176
... Reset on loss of lock 0 No reset on loss of lock Note: In external clock mode, the LOLRE bit has no effect. 9 MFD1 MFD0 LOCRE 0010_0001 R FWKUP — STPMD1 0000_0000 R IPSBAR + 0x0012_0000 Table 9-4. SYNCR Field Descriptions Description RFD2 RFD1 RFD0 STPMD0 — — R/W R Freescale Semiconductor ...
Page 177
... See table in MFD bit description. Changing RFD[2:0] does not affect the PLL or cause a relock delay. Changes in clock frequency are synchronized to the next falling edge of the current system clock. To avoid surpassing the allowable system operating frequency, write to RFD[2:0] only when the LOCK bit is set. Freescale Semiconductor Description (( 1 in normal PLL mode ...
Page 178
... Figure 9-4. Synthesizer Status Register (SYNSR) 9-8 Description Operation During Stop Mode System PLL Clocks 00 Disabled Enabled 01 Disabled Enabled 10 Disabled Disabled 11 Disabled Disabled PLLREF LOCKS LOCK See note 2 R IPSBAR + 0x0012_0002 . OSC CLKOUT Enabled Enabled Enabled Disabled Enabled Disabled Disabled Disabled LOCS — 000 Freescale Semiconductor ...
Page 179
... PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset. If operating in external clock mode, LOCK remains cleared after reset. 1 PLL locked 0 PLL not locked Freescale Semiconductor Table 9-5. SYNSR Field Descriptions Description Table 9-6. ...
Page 180
... Table 9-6. System Clock Modes Clock Mode External clock mode 1:1 PLL mode Normal PLL mode with external clock reference Normal PLL mode with crystal reference Table 27-8). The values of CLKMOD[1:0] are PLL Options × 2(MFD + 2)/ sys ref sys ref sys ref 1 RFD Freescale Semiconductor ...
Page 181
... For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of 4 MHz to 18 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL. Freescale Semiconductor CAUTION NOTE ...
Page 182
... The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source. 9-12 8-MHz CRYSTAL CONFIGURATIO MΩ 470 Ω EXTAL XTAL V SSSYN RS RF Figure 9-5. Crystal Oscillator Example Figure to see how these Freescale Semiconductor ...
Page 183
... The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided. Freescale Semiconductor Table 9-8. ...
Page 184
... Set Relaxed Lock Condition and Notify System of Lock Condition Figure 9-6. Lock Detect Sequence Figure 9-6 shows the sequence Reference Count ≠ Feedback Count Count Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = Same Count/Compare Sequence Freescale Semiconductor ...
Page 185
... Before Failure PLL PLL External External clock 1 The LOC circuit monitors the reference and feedback inputs to the PFD. See Freescale Semiconductor Section 29.4.2, “Reset Status Register NOTE Table 9-9. Loss of Clock Summary Reference Failure Alternate Clock 1 Selected by LOC Circuit Until Reset ...
Page 186
... C LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit until reference regained 0–> 0–> 1–> Block LOCS and LOCKS until clock and lock respectively regain; enter SCM regardless of LOCEN bit — — — Freescale Semiconductor ...
Page 187
... Off On 0 Lose lock NRM Off On 1 Lose lock NRM NRM NRM Off X X Lose lock, f.b. clock, reference clock Freescale Semiconductor PLL Action MODE During Stop Out Regain NRM Lose reference Stuck clock or no lock regain Lose reference NRM clock, ...
Page 188
... REF mode not K 1 entered during stop — — — Wakeup without lock ‘LK 1 ‘ Wakeup without lock Wakeup without lock — — — ‘LC ‘LK 1 ‘ Wakeup without lock Wakeup without lock 0 0–> ‘LC 1 Freescale Semiconductor ...
Page 189
... NRM NRM REF SCM Off X 0 PLL disabled SCM Off X 1 PLL disabled SCM Freescale Semiconductor PLL Action MODE During Stop Out — — NRM Lose lock or clock RESET RESET RESET — — NRM Lose clock RESET Lose lock Stuck Lose lock, regain NRM — ...
Page 190
... CLK is never expected to regain 9-20 PLL Action MODE During Stop Out — — SCM Lose reference SCM clock Comments Freescale Semiconductor ...
Page 191
... For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see Freescale Semiconductor 10-1 ...
Page 192
... Interrupt Level ICR[IL] 10-2 Definition” for more information on the stack frame format). Determination.” Table 10-1, which orders the interrupt levels/priorities from highest Table 10-1. Interrupt Priority Scheme Priority Supported Interrupt Sources ICR[IP #8– — (Mid-point) #7 (IRQ7 #8– Freescale Semiconductor ...
Page 193
... Prioritization • Vector Determination during IACK 10.1.1.1 Interrupt Recognition The interrupt controller continuously examines the request sources and the interrupt mask register to determine if there are active requests. This is the recognition phase. Freescale Semiconductor Priority Supported Interrupt Sources ICR[IP] 7–4 #8–63 6 — ...
Page 194
... The nomenclature <reg_name>H and <reg_name>L is used to reference these values. 10-4 then vector_number = 65 then vector_number = 66 then vector_number = 72 then vector_number = 73 then vector_number = 126 Freescale Semiconductor ...
Page 195
... ICR48 0x74 ICR52 0x78 ICR56 0x7C ICR60 Freescale Semiconductor Table 10-3. The offsets listed start from the base address 1 Section 10.3.7, “Software and Level n L1IACK–L7IACK)" for more information Bits[23:16] Interrupt Pending Register High (IPRH), [63:32] Interrupt Pending Register Low (IPRL), [31:1] ...
Page 196
... Figure 10-1. Interrupt Pending Register High (IPRHn) 10-6 Bits[23:16] Reserved Figure 10-1 and Figure 10-2, are each 32 bits in size, and provide a bit INT[63:48] 0000_0000_0000_0000 R INT[47:32] 0000_0000_0000_0000 R IPSBAR + 0xC00, 0xD00 Bits[15:8] Bits[7:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 16 0 Freescale Semiconductor ...
Page 197
... The IMRn can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability. Freescale Semiconductor Table 10-4. IPRHn Field Descriptions Description ...
Page 198
... Field Reset R/W 15 Field Reset R/W Figure 10-4. Interrupt Mask Register Low (IMRLn) 10-8 INT_MASK[63:48] 1111_1111_1111_1111 R/W INT_MASK[47:32] 1111_1111_1111_1111 R/W IPSBAR + 0xC08, 0xD08 Table 10-6. IMRHn Field Descriptions Description INT_MASK[31:16] 1111_1111_1111_1111 R/W INT_MASK[16:1] 1111_1111_1111_1111 R/W IPSBAR + 0xC0C, 0xD0C MASKALL Freescale Semiconductor ...
Page 199
... INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is cleared by reset. Freescale Semiconductor Table 10-7. IMRLn Field Descriptions Description NOTE ...
Page 200
... INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source 0 — Reserved, should be cleared. 10-10 INTFRCH[63:48] 0000_0000_0000_0000 R/W INTFRCH[47:32] 0000_0000_0000_0000 R/W IPSBAR + 0xC10, 0xD10 Description INTFRCL[31:16] 0000_0000_0000_0000 R/W INTFRCL[16:1] 0000_0000_0000_0000 R/W IPSBAR + 0xC14, 0xD14 Description — Freescale Semiconductor ...