MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 509

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

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2
Freescale Semiconductor
0x10_001C
0x10_002C
0x10_003C
0x10_004C
0x10_005C
0x10_007C
0x10_0014
0x10_0018
0x10_0020
0x10_0024
0x10_0028
0x10_0030
0x10_0034
0x10_0038
0x10_0040
0x10_0044
0x10_0048
0x10_0050
0x10_0054
0x10_0058
0x10_0060
IPSBAR +
S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle
termination transfer error.
Writing to reserved address locations has no effect and reading returns 0s.
Offset
–
PORTTDP/SETTD
PORTASP/SETAS
PORTEP/SETE
PORTAP/SETA
PORTJP/SETJ
PBCDPAR
PEHLPAR
PUAPAR
DDRAS
DDRTD
CLRAS
CLRTD
PJPAR
31–24
DDRA
DDRE
DDRJ
CLRA
CLRE
CLRJ
Table 26-2. Ports Module Memory Map (continued)
PORTDDP/SETDD
PORTQSP/SETQS
PORTUAP/SETUA
PORTBP/SETB
PORTFP/SETF
Port Pin Data/Set Data Registers
Port Clear Output Data Registers
PSDPAR
PQSPAR
DDRDD
DDRQS
DDRUA
CLRDD
CLRQS
CLRUA
Port Pin Assignment Registers
PFPAR
DDRB
23–16
DDRF
Port Data Direction Registers
CLRB
CLRF
Reserved
(Reserved on MCF521x)
(Reserved on MCF521x)
(Reserved on MCF521x)
PORTEHP/SETEH
PORTSDP/SETSD
2
PORTGP/SETG
PORTCP/SETC
Reserved
PTCPAR
DDREH
DDRSD
CLREH
CLRSD
DDRG
DDRC
CLRG
CLRC
15–8
2
Reserved
Reserved
Reserved
PASPAR
PEPAR
PORTTCP/SETTC
PORTELP/SETEL
2
2
2
PORTDP/SETD
PORTHP/SETH
PTDPAR
General Purpose I/O Module
DDREL
DDRTC
CLRTC
CLREL
DDRD
DDRH
CLRD
CLRH
7–0
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
26-9
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