MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 306

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DMA Controller Module
16.4.5
In response to an event, the DMA controller writes to the appropriate DSRn bit,
to DSRn[DONE] results in action.
Table 16-4
16-10
14–0
Bits
Bits
15
7
6
5
4
3
2
DMA Status Registers (DSR0–DSR3)
describes DSRn fields.
Name
Name
BED
REQ
BES
CE
AT
—
—
—
AT is available only if MPARK[BCR24BIT] = 1.
DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer
or only the final transfer.
0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the
1 Final transfer (when BCR reaches zero). For dual-address transfer, the acknowledge information
Reserved, should be cleared.
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size,
or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing
a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
Address
result of an external request.
is displayed for both the read and write cycles.
Reset
Field
R/W
Table 16-3. DCRn Field Descriptions (continued)
—
7
Figure 16-9. DMA Status Registers (DSRn)
Table 16-4. DSRn Field Descriptions
CE
6
IPSBAR + 0x110, 0x150, 0x190, 0x1D0
BES
5
BED
0000_0000
4
Description
Description
R/W
—
3
REQ
2
BSY
1
Figure
DONE
0
Freescale Semiconductor
16-9. Only a write