MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 81

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

3.2
The following table and sections explain the MAC registers:
3.2.1
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
Freescale Semiconductor
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDM: 0x804 (MACSR)
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
0x80A
0x80B
BDM
0x804
0x805
0x806
0x807
0x808
0x809
W
31–12
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
PAVn
11–8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1
Memory Map/Register Definition
MAC Status Register (MACSR)
MAC Status Register (MACSR)
MAC Address Mask Register (MASK)
MAC Accumulator 0 (ACC0)
MAC Accumulator 0,1 Extension Bytes (ACCext01)
MAC Accumulator 2,3 Extension Bytes (ACCext23)
MAC Accumulator 1 (ACC1)
MAC Accumulator 2 (ACC2)
MAC Accumulator 3 (ACC3)
Reserved, must be cleared.
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the
general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR
instruction or the accumulator is loaded directly.
Bit 11: Accumulator 3
...
Bit 8: Accumulator 0
Chapter 43, “Debug Module.”
Figure 3-2. MAC Status Register (MACSR)
Register
Table 3-2. MACSR Field Descriptions
Table 3-1. EMAC Memory Map
Description
Width
(bits)
32
32
32
32
32
32
32
32
PAVn
Access
Enhanced Multiply-Accumulate Unit (EMAC)
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OMC S/U
0
7
0xFFFF_FFFF
0x0000_0000
Reset Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
6
Access: Supervisor read/write
F/I
0
5
R/T N
0
4
Section/Page
BDM read/write
0
3.2.1/3-3
3.2.2/3-5
3.2.3/3-6
3.2.4/3-7
3.2.4/3-7
3.2.3/3-6
3.2.3/3-6
3.2.3/3-6
3
Z
0
2
V EV
1
0
3-3
0
0