MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 202

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Interrupt Controller Modules
10.3.6
Each ICRnx specifies the interrupt level (1-7) and the priority within the level (0-7). All ICRnx registers
can be read, but only ICRn8 to ICRn63 can be written. It is the responsibility of the software to program
the ICRnx registers with unique and non-overlapping level and priority definitions. Failure to program the
ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely
unused, the ICRnx value can remain in its reset (and disabled) state.
10-12
Bits
Bits
6–4
3–0
7–6
5–3
2–0
Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))
LEVEL
Name
Name
PRI
—
IP
IL
Address
Interrupt level. Represents the interrupt level currently being acknowledged.
Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being
acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
Reserved, should be cleared.
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level
assignment. 000b represents the lowest priority and 111b represents the highest. For the fixed level
interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as
000b.
Reset
Field
R/W
Table 10-11. IACKLPRn Field Descriptions (continued)
Note: It is the responsibility of the software to program the ICRnx registers
with unique and non-overlapping level and priority definitions. Failure to
program the ICRnx registers in this manner can result in undefined behavior.
If a specific interrupt request is completely unused, the ICRnx value can
remain in its reset (and disabled) state.
7
Figure 10-9. Interrupt Control Register (ICRnx)
—
Table 10-12. ICRnx Field Descriptions
See
6
Table 10-2
R/W (Read only for ICRn1-ICRn7)
5
and
IL
0000_0000
Table 10-3
Description
Description
3
for register offsets
2
IP
Freescale Semiconductor
0