MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 351

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

17.5.11 Full Duplex Flow Control
Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon
detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] set) with flow
control (RCR[FCE] set). The FEC detects a pause frame when the fields of the incoming frame match the
pause frame specifications, as shown in
frame should indicate that the frame is valid.
The receiver and microcontroller modules perform PAUSE frame detection. The microcontroller runs an
address recognition subroutine to detect the specified pause frame destination address, while the receiver
detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the
FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer
begins to increment. The pause timer uses the transmit backoff timer hardware for tracking the appropriate
collision backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is cleared
allowing MAC data frame transmission to resume. The receive flow control pause status bit
(TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow control pause
(TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets TCR[GTS] internally. When
the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts and the
pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally.
You must specify the desired pause duration in the OPD register.
Freescale Semiconductor
48-bit Destination Address
Table 17-37. Destination Address to 6-Bit Hash (continued)
48-bit Source Address
16-bit PAUSE Duration
16-bit Opcode
DDFF_FFFF_FFFF
FDFF_FFFF_FFFF
9DFF_FFFF_FFFF
BDFF_FFFF_FFFF
16-bit Type
Table 17-38. PAUSE Frame Field Specification
48-bit DA
Table
17-38. In addition, the receive status associated with the
6-bit Hash
0x0180_C200_0001 or Physical Address
(in hex)
0x3C
0x3D
0x3E
0x3F
0x0000 – 0xFFFF
0x8808
0x0001
Hash Decimal
Any
Value
60
61
62
63
Fast Ethernet Controller (FEC)
17-41