MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 365

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.2.2
The 16-bit read/write PMRn contains the timer modulus value loaded into the PIT counter when the count
reaches 0x0000 and the PCSRn[RLD] bit is set.
When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is immediately
loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into
the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch.
Reset initializes PMRn to 0xFFFF.
19.2.3
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads
is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.
Freescale Semiconductor
IPSBAR
Field
Offset:
Field
15–0
RLD
Reset
EN
PM
1
0
W
R
0x15_0002 (PMR0)
0x16_0002 (PMR1)
0x17_0002 (PMR2)
0x18_0002 (PMR3)
Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches
0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This
bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the
PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the
counter. Reading this field returns the value written.
15
1
PIT Modulus Register (PMRn)
PIT Count Register (PCNTRn)
14
1
13
1
Table 19-3. PCSRn Field Descriptions (continued)
12
1
Figure 19-3. PIT Modulus Register (PMRn)
11
Table 19-4. PMRn Field Descriptions
1
10
1
1
9
Description
Description
1
8
PM
1
7
1
6
Programmable Interrupt Timers (PIT0–PIT3)
1
5
4
1
1
3
Access: Supervisor
1
2
1
1
read/write
19-5
1
0