MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 310
MCF5282CVM66
Manufacturer Part Number
MCF5282CVM66
Description
Manufacturer
Freescale
Datasheet
1.MCF5282CVM66.pdf
(766 pages)
Specifications of MCF5282CVM66
Cpu Family
MCF528x
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Interface Type
CAN/I2C/QSPI/UART
Total Internal Ram Size
64KB
# I/os (max)
150
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
3.3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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DMA Controller Module
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address,
but not exceeding the configured size.
16.5.4.2 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another device.
DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the
decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending,
the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCRn[AA] = 1,
the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the
core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See
Section 8.5.3, “Bus Master Park Register
16.5.5
An unsuccessful transfer can terminate for one of the following reasons:
16-14
•
•
•
Error conditions—When the processor encounters a read or write cycle that terminates with an
error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer
is halted. If the error occurred in a write cycle, data in the internal holding register is lost.
Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal. The
processor can read DSRn to determine whether the transfer terminated successfully or with an
error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits.
Termination
(MPARK).”
Freescale Semiconductor
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