MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 228

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

External Interface Module (EIM)
Basic operation of the bus is a three-clock bus cycle:
13.4.2
The data transfer operation is controlled by an on-chip state machine. Each bus clock cycle is divided into
two states. Even states occur when CLKOUT is high and odd states occur when CLKOUT is low. The state
transition diagram for basic and fast termination read and write cycles are shown in
13-4
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the external
3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold
device provides data and is sampled at the rising edge at the end of the second bus clock. This data
is concurrent with TA, which is also sampled at the rising edge of the clock.
During a write, the ColdFire device drives data from the rising clock edge at the end of the first
clock to the rising clock edge at the end of the bus cycle. Wait states can be added between the first
and second clocks by delaying the assertion of TA. TA can be configured to be generated internally
through the CSCRs. If TA is not generated internally, the system must provide it externally.
time for address, attributes and write data.
write operations.
0
1
Multiple
0
1
Multiple
0
1
Multiple
Data Transfer Cycle States
Number of CSCR Matches
Table 13-2. Accesses by Matches in CSCRs and DACRs
0
0
0
1
1
1
Multiple
Multiple
Multiple
Number of DACR Matches
Figure 13-6
and
External
Defined by CSCR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Figure 13-8
Type of Access
show the basic read and
Figure
Freescale Semiconductor
13-4.