MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 541

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

When the QADC enters debug mode while a queue is active, the current CCW location of the queue
pointer is saved.
Debug mode:
Although the QADC saves a pointer to the next CCW in the current queue, software can force the QADC
to execute a different CCW by reconfiguring the QADC. When the QADC exits debug mode, it looks at
the queue operating modes, the current queue pointer, and any pending trigger events to decide which
CCW to execute.
28.3.2
The QADC enters a low-power idle state whenever the QSTOP bit is set or the CPU enters low-power stop
mode.
QADC stop:
Because the bias currents to the analog circuit are turned off in stop mode, the QADC requires some
recovery time (t
28.4
The QADC uses the external signals shown in
support up to 18 channels when external multiplexing is used (including internal channels). All of the
channel signals also have some general-purpose input or input/output (GPIO) functionality. In addition,
there are also two analog reference signals and two analog submodule power signals.
The QADC has external trigger inputs and multiplexer outputs that are shared with some of the analog
input signals.
28.4.1
The four port QA signals can be used as analog inputs or as a bidirectional 4-bit digital input/output port.
Freescale Semiconductor
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If during the execution of the current conversion, the queue operating mode for the active queue is
changed, or a queue 2 abort occurs, the QADC freezes immediately.
Stops the analog clock
Holds the periodic/interval timer in reset
Prevents external trigger events from being captured
Keeps all QADC registers and RAM accessible
Disables the analog-to-digital converter, effectively turning off the analog circuit
Aborts the conversion sequence in progress
Makes the data direction register (DDRQA), port data registers (PORTQA and PORTQB), control
registers (QACR2, QACR1, and QACR0) and the status registers (QASR1 and QASR0) read-only.
Only the module configuration register (QADCMCR) remains writable.
Makes the RAM inaccessible, so that valid data cannot be read from RAM (result word table and
CCW) or written to RAM (result word table and CCW)
Resets QACR1, QACR2, QASR0, and QASR1
Holds the QADC periodic/interval timer in reset
Signals
Stop Mode
Port QA Signal Functions
SR
) to stabilize the analog circuits.
Figure
28-2. There are eight channel/port signals that can
Queued Analog-to-Digital Converter (QADC)
28-3