MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 487

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

25.4.11.3 Auto-Power Save Mode
Auto-power save mode enables normal operation with optimized power savings. Once the auto-power
save (APS) bit in CANMCR is set, the FlexCAN looks for a set of conditions in which there is no need for
its clocks to be running. If these conditions are met, the FlexCAN stops its clocks, thus saving power. The
following conditions will activate auto-power save mode.
While its clocks are stopped, if the FlexCAN senses that any one of the aforementioned conditions is no
longer true, it restarts its clocks. The FlexCAN then continues to monitor these conditions and
stops/restarts its clocks accordingly.
25.4.12 Interrupts
The module can generate up to 19 interrupt sources (16 interrupts due to message buffers and 3 interrupts
due to Bus-off, Error and Wake-up). Each one of the message buffers can be an interrupt source, if its
corresponding IMASK bit is set.
There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the
buffer is initialized for either transmission or reception, and thus its interrupt routine can be fixed at
compilation time. Each of the buffers is assigned a bit in the IFLAG register. The bit is set when the
corresponding buffer completes a successful transmission or reception, and cleared when the CPU reads
the interrupt flag register (IFLAG) while the associated bit is set, and then writes it back as ‘1’ (and no new
event of the same type occurs between the read and the write actions).
The other 3 interrupt sources (Bus-off, Error and Wake-up) act in the same way, and are located in the Error
& Status register. The Bus-off and Error interrupt mask bits are located in the CANCTRL0 register, and
the Wake-up interrupt mask bit is located in the CANMCR.
25.5
This section describes the registers in the FlexCAN module.
Programming the FlexCAN control registers is typically done during system initialization, prior to the
FlexCAN becoming synchronized with the CAN bus. The configuration registers can be changed after
synchronization by halting the FlexCAN module. This is done when the user sets the HALT bit in the
FlexCAN module configuration register (CANMCR). The FlexCAN responds by setting the
CANMCR[NOTRDY] bit. Additionally, the control registers can be modified while the MCU is in
background debug mode.
Freescale Semiconductor
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No Rx/Tx frame in progress.
No transfer of Rx/Tx frames to and from an SMB, and no Tx frame awaiting transmission in any
message buffer.
No CPU access to the FlexCAN module.
The FlexCAN is not in debug mode, low-power stop mode, or the bus off state.
Programmer’s Model
The FlexCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provided if
the programming does not meet CAN protocol requirements.
NOTE
FlexCAN
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