MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 289

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

15.2.4
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this
sequence with the following procedure:
Freescale Semiconductor
SDRAM_CS[0] or [1]
(DCR[COC] = 0)
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable
3. Issue a
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
6. Issue the
action is taken on the SDRAMs. This is normally around 100 µs.
or
Wait the time (determined by t
the
that mode register settings are driven on the SDRAM address bus, so care must be taken to change
DMR[BAM] if the mode register configuration does not fall in the address range determined by
the address mask bits. After the mode register is set, DMR mask bits can be restored to their
desired configuration.
CLKOUT
DRAMW
REF
SRAS
SCAS
SCKE
MRS
Initialization Sequence
commands.
PALL
to execute properly
MRS
command to the SDRAMs by setting DACR[IP] and accessing a SDRAM location.
PALL
command by setting DACR[IMRS] and accessing a location in the SDRAM. Note
t
RCD
MRS
= 2
command, determine if the DMR mask bits need to be modified to allow
Figure 15-9. Self-Refresh Operation
SELF
RP
Refresh
) before any other execution.
Active
Self-
SELFX
t
RC
= 6
Synchronous DRAM Controller Module
Possible
ACTV
First
PALL
15-17