EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 598

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–86
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
1.8-V SSTL
CLASS I
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
Table 1–52. EP3SL50 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–53. EP3SL50 Column Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Strength
Current
12mA
16mA
12mA
16mA
8mA
8mA
Table 1–53
adder values that should be added to GCLK values. These adder values
are used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III.
Table 1–53
Regional Clock.
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Industrial
Clock Parameter
PLL
PLL
PLL
PLL
PLL
PLL
—
—
Fast Model
t
t
t
t
t
t
t
t
t
t
t
t
through
specifies EP3SL50 Column Pin delay adders when using the
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
Commercial
1.912
1.868
Industrial Commercial
Table 1–54
—
—
—
—
—
—
—
—
—
—
—
—
Fast Model
V
2.891
2.846
1.1V
show EP3SL50 regional clock (RCLK)
CCL
-2
2.662
1.513
2.657
1.508
2.658
1.509
2.666
1.517
2.662
1.513
2.658
1.509
=
V
3.176
3.127
1.1V
CCL
-3
=
4.331 4.862 5.160 5.008 5.159
2.489 2.808 2.891 2.847 2.828
4.321 4.851 5.148 4.997 5.148
2.479 2.797 2.879 2.836 2.817
4.323 4.853 5.151 4.999 5.150
2.481 2.799 2.882 2.838 2.819
4.338 4.871 5.169 5.017 5.168
2.496 2.817 2.900 2.856 2.837
4.330 4.861 5.159 5.007 5.158
2.488 2.807 2.890 2.846 2.827
4.323 4.853 5.151 4.999 5.150
2.481 2.799 2.882 2.838 2.819
V
1.1V
CCL
-2
3.476
3.442
V
1.1V
CCL
-4
=
=
V
1.1V
CCL
-3
3.309
3.285
V
1.1V
CCL
=
Altera Corporation
=
V
-4L
November 2007
1.1V
CCL
-4
V
3.291
0.9V
3.29
=
CCL
=
V
1.1V
CCL
Units
=
-4L
ns
ns
V
0.9V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns