EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 378

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Fast Passive Parallel Configuration
11–18
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
t
t
t
t
t
f
t
t
t
t
t
Symbol
DSU
DH
CH
CL
CLK
MAX
R
CD2UM
CD2CU
CD2UMC
Table 11–5. FPP Timing Parameters for Stratix III Devices
This information is preliminary.
You should use these timing parameters when the decompression and design security features are not used.
This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for
starting up the device.
Table
Data setup time before rising edge on
Data hold time after rising edge on
DCLK
DCLK
DCLK
DCLK
Input rise time
Input fall time
CONF_DONE
CONF_DONE
CONF_DONE
CLKUSR
11–5:
high time
low time
frequency
period
option on
high to user mode
high to
high to user mode with
Parameter
Figure 11–7
using a MAX II device as an external host. This waveform shows the
timing when the decompression and/or the design security feature are
enabled.
CLKUSR
enabled
(4)
shows the timing waveform for FPP configuration when
DCLK
DCLK
t
CD2CU
4 × maximum
DCLK
×
Minimum
Notes
period)
CLKUSR
10
20
—
—
—
+ (4,436
5
0
4
4
period
(1),
(2)
(Part 2 of 2)
Maximum
100
100
40
40
—
—
—
—
—
—
—
Altera Corporation
November 2007
Units
MHz
ns
ns
ns
ns
ns
ns
ns
μs
—
—