EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 400

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Passive Serial Configuration
Figure 11–17. PS Configuration Using a USB Blaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV Cable
Notes to
(1)
(2)
(3)
11–40
Stratix III Device Handbook, Volume 1
You should connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (V
ByteBlaster II, or ByteBlasterMV cable.
You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used
on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you are
also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK.
Pin 6 of the header is a V
V
ByteBlasterMV cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to
nCE when it is used for active serial programming, otherwise it is a no connect.
CCIO
Figure
. Refer to the
11–17:
V
CC
10 kΩ
10 kΩ
(1)
(2)
V
(2)
CC
MasterBlaster Serial/USB Communications Cable Data Sheet
(1)
V
CC
10 kΩ
(1)
IO
a time on the device's DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high. The CONF_DONE pin must
have an external 10-kΩ pull-up resistor in order for the device to
initialize.
When using a download cable, setting the Auto-restart configuration
after error option does not affect the configuration cycle because you
must manually restart configuration in the Quartus II software when an
error occurs. Additionally, the Enable user-supplied start-up clock
(CLKUSR) option has no affect on the device initialization since this
option is disabled in the SOF when programming the device using the
Quartus II programmer and download cable. Therefore, if you turn on
the CLKUSR option, you do not need to provide a clock on CLKUSR when
you are configuring the device with the Quartus II programmer and a
download cable.
devices using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV cable.
reference voltage for the MasterBlaster output driver. V
V CCPGM
GND
GND
MSEL2
MSEL1
MSEL0
nCE
DCLK
DATA0
nCONFIG
Stratix III Device
Figure 11–17
CONF_DONE
nSTATUS
nCEO
N.C.
shows PS configuration for Stratix III
V
CC
10 kΩ
(1)
V
CC
10 kΩ
(1)
Pin 1
10-Pin Male Header
Download Cable
IO
(PS Mode)
Shield
GND
should match the device's
for this value. In the
V
V
CC
IO
(3)
GND
Altera Corporation
November 2007
IO
pin),