EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 155

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–4. Regional Clock Networks (EP3SL200, EP3SE260, and EP3SL340 Devices)
Notes to
(1)
Altera Corporation
November 2007
The corner RCLKs [64..87] can only be fed by their respective corner PLL outputs. See
Figure
6–4:
CLK[0..3]
L1
L2
L3
L4
Periphery Clock Networks
Periphery clock (PCLK) networks are a collection of individual clock
networks driven from the periphery of the Stratix III device. Clock
outputs from the DPA block, horizontal I/O pins, and internal logic can
drive the PCLK networks. The EP3SL50, EP3SL70, and EP3SE50 devices
contain 56 PCLKs; the EP3SL110, EP3SL150, EP3SL200, EP3SE80, and
EP3SE110 devices contain 88 PCLKs; the EP3SE260 device contains 112
PCLKs, and the EP3SL340 device contains 116 PCLKs. These PCLKs have
higher skew compared to GCLK and RCLK networks and can be used
instead of general purpose routing to drive signals into and out of the
Stratix III device.
Clocking Regions
Stratix III devices provide up to 104 distinct clock domains (16 GCLKs +
88 RCLKs) in the entire device. You can utilize these clock resources to
form the following four different types of clock region:
■
■
■
■
RCLK[82..87]
RCLK[64..69]
RCLK[0..5]
RCLK[6..11]
Entire device clock region
Regional clock region
Dual-regional clock region
Sub-regional clock region
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
CLK[12..15]
Q1
Q4
CLK[4..7]
T1
B1
T2
B2
Q2
Q3
Clock Networks and PLLs in Stratix III Devices
RCLK[76..81]
RCLK[32..37]
RCLK[70..75]
RCLK[38..43]
Stratix III Device Handbook, Volume 1
R1
R2
R3
R4
CLK[8..11]
Table 6–9
Note (1)
for connectivity.
6–5