EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 444

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1 Boundary-Scan Register
13–6
Stratix III Device Handbook, Volume 1
Boundary-Scan Cells of a Stratix III Device I/O Pin
The Stratix III device three-bit boundary-scan cell (BSC) consists of a set
of capture registers and a set of update registers. The capture registers can
connect to internal device data via the OUTJ, OEJ, and PIN_IN signals,
while the update registers connect to external data through the PIN_OUT,
and PIN_OE signals.
The global control signals for the IEEE Std. 1149.1 BST registers (such as
shift, clock, and update) are generated internally by the TAP controller.
The MODE signal is generated by a decode of the instruction register. The
HIGHZ signal is high when executing the HIGHZ instruction. The data
signal path for the boundary-scan register runs from the serial data in
(SDI) signal to the serial data out (SDO) signal. The scan register begins at
the TDI pin and ends at the TDO pin of the device.
EP3SE110
EP3SE260
Table 13–2. Stratix III Boundary-Scan Register Length
Device
Boundary-Scan Register Length
2274
2970
Altera Corporation
November 2007