EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 534

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Switching Characteristics
1–22
Stratix III Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
DDR3 SDRAM
DDR2 SDRAM
DDR SDRAM
QDRII+ SRAM
QDRII SRAM
RLDRAM II
Table 1–26. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate
Controller
Memory Standards
Numbers are based on half-rate controller and are preliminary until characterization is final.
Performance is based on 0.9-V core voltage. At 1.1-V core voltage, the -4L speed grade devices have the same
performance as the -4 speed grade devices.
Left/right I/O banks have lower maximum performance than the top/bottom I/O banks due to the left/right I/Os
having higher pin capacitance to support the LVDS I/O standard.
This applies for interfaces with both modules and components.
DDR3/DDR2 SDRAM interfaces above 333 MHz requires the use of the deskew circuitry pending characterization.
Support will be evaluated after characterization.
Stratix III FPGAs support QDRII+ devices with 2.5 cycle read latency. Stratix III FPGAs do not support QDRII+
devices with 2.0 cycle read latency.
This applies to QDRII SRAM and RLDRAM II devices running at 1.5-V and 1.8-V I/O voltages.
Table
Notes (1)
(8)
(8)
(4)
1–26:
(7)
(4)
(4)
Use
analysis.
Bottom
400
400
–2 Speed Grade
Banks
Top/
200
350
350
400
I/O
(5)
(5)
Table 1–26
(MHz)
Banks
Right
Left/
300
300
200
300
300
300
I/O
(3)
through
Bottom
–3 Speed Grade
Banks
Top/
333
333
200
300
300
300
I/O
(MHz)
Table 1–31
TBD
Banks
Right
Left/
267
200
250
250
250
I/O
(3)
(6)
to perform memory interface timing
Bottom
–4 Speed Grade
Banks
Top/
333
333
200
300
300
300
I/O
(MHz)
TBD
Banks
Right
Left/
267
200
250
250
250
I/O
(3)
(6)
Altera Corporation
Bottom
-4L Speed Grade
Banks
Top/
200
200
167
November 2007
I/O
—
—
—
(MHz)
(2)
Banks
Right
Left/
167
167
133
I/O
—
—
—