EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 446

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1 Boundary-Scan Register
13–8
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
User I/O pins
Dedicated clock
input
Dedicated input
(3)
Dedicated
bidirectional
(open drain)
Dedicated
bidirectional
Dedicated
output
Table 13–3. Stratix III Device Boundary Scan Cell Descriptions
Pin Type
TDI, TDO, TMS, TCK, TRST, all V
No Connect (N.C.).
This includes pins PLL_ENA, nCONFIG, MSEL0, MSEL1, MSEL2, nCE, PORSEL, and nIO_PULLUP.
This includes pins CONF_DONE and nSTATUS.
This includes pin DCLK.
This includes pin nCEO.
(6)
Table
(5)
(4)
13–3:
Register
Capture
Output
OUTJ
OUTJ
OUTJ
0
0
0
Table 13–3
boundary-scan cells within Stratix III devices.
Captures
Register
Capture
CC
OEJ
OEJ
OEJ
OE
and GND pin types, VREF, and TEMP_DIODE pins do not have BSCs.
1
1
0
describes the capture and update register capabilities of all
Register
PIN_IN PIN_OUT
PIN_IN
PIN_IN
PIN_IN
PIN_IN
Capture
Input
0
Register
N.C.
N.C.
N.C.
N.C.
N.C.
Update
Output
(2)
(2)
(2)
(2)
(2)
Note (1)
Register
PIN_OE
N.C.
N.C.
N.C.
N.C.
N.C.
Update
Drives
OE
(2)
(2)
(2)
(2)
(2)
Register
N.C.
N.C.
N.C.
N.C.
N.C.
Update
Input
INJ
(2)
(2)
(2)
(2)
(2)
Altera Corporation
NA
PIN_IN
clock network or
logic array
PIN_IN
control logic
PIN_IN
configuration
control
PIN_IN
configuration
control and
drives to output
buffer
OUTJ
output buffer
November 2007
Comments
drives to
drives to
drives to
drives to
drives to
OUTJ