EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 320
EP3SL150F780I3N
Manufacturer Part Number
EP3SL150F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheet
1.EP3SL110.pdf
(904 pages)
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Differential Transmitter
Differential
Transmitter
9–4
Stratix III Device Handbook, Volume 1
Note to
(1)
(2)
(3)
EP3SE80
EP3SE110
EP3SE260
Table 9–2. LVDS Channels (Emulated) Supported in Stratix III Device Column I/O Banks
Device
LVDS input buffers at column I/O banks are true LVDS input buffers. All user I/Os, including I/Os with true LVDS
input buffers, can be configured as emulated LVDS output buffers.
The EP3SL200 and EP3SE260 FPGAs are offered in the H780 package, instead of the F780 package.
The EP3SL340 FPGA is offered in the H1152 package, instead of the F1152 package.
Table
FineLine BGA
9–2:
484 - Pin
—
—
—
The Stratix III transmitter has dedicated circuitry to provide support for
LVDS signaling. The dedicated circuitry consists of a differential buffer,
a serializer, and a shared analog PLL (left/right PLL). The differential
buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The
serializer takes up to 10-bits wide parallel data from the FPGA core,
clocks it into the load registers, and serializes it using shift registers
clocked by the left/right PLL before sending the data to the differential
buffer. The most significant bit (MSB) of the parallel data is transmitted
first.
The load and shift registers are clocked by the load enable (load_en)
signal and the diffioclk (clock running at serial data rate) signal
generated from PLL_Lx (left PLL) or PLL_Rx (right PLL). The
serialization factor can be statically set to ×4, ×6, ×7, ×8, or ×10 using the
Quartus
serialization factor setting.
transmitter.
64Rx/Tx + 64Tx
64Rx/Tx + 64Tx
64Rx/Tx + 64Tx
FineLine BGA
780 - Pin
®
II software. The load enable signal is derived from the
(2)
96Rx/Tx + 96Tx
96Rx/Tx + 96Tx
96Rx/Tx + 96Tx
FineLine BGA
1152 - Pin
Figure 9–2
is a block diagram of the Stratix III
128Rx/Tx + 128Tx
FineLine BGA
1517 - Pin
—
—
Altera Corporation
Note (1)
November 2007
FineLine BGA
1780 - Pin
—
—
—
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