EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 331

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clocking
Figure 9–13. LVDS/DPA Clocks in Stratix III Devices with Center PLLs
Altera Corporation
November 2007
4
4
4
2
2
4
LVDS
Clock
LVDS
Clock
PLL_L2
Center
PLL_L3
Center
Clock
Clock
DPA
DPA
The left/right PLLs feed into the differential transmitter and receive
channels through the LVDS and DPA clock network. The center left/right
PLLs can clock the transmitter and receive channels above and below
them. The corner left/right PLLs can drive I/Os in the banks adjacent to
them.
in Stratix III devices. More information on PLL clocking restrictions can
be found in
Figure 9–13
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
“Differential Pin Placement Guidelines” on page
Quadrant
Quadrant
and
Figure 9–14
Quadrant
Quadrant
show center and corner PLL clocking
Stratix III Device Handbook, Volume 1
Clock
Clock
DPA
DPA
PLL_R2
PLL_R3
Center
Center
LVDS
Clock
LVDS
Clock
4
2
2
4
9–21.
4
4
9–15