EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 372

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Fast Passive Parallel Configuration
11–12
Stratix III Device Handbook, Volume 1
1
Data is continuously clocked into the target device until CONF_DONE goes
high. The CONF_DONE pin goes high one byte early in parallel
configuration (FPP) modes. The last byte is required for serial
configuration (AS and PS) modes. After the device has received the next
to last byte of the configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The
CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for
the device to initialize.
In Stratix III devices, the initialization clock source is either the internal
oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If you use the
internal oscillator, the Stratix III device provides itself with enough clock
cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
You can also synchronize initialization of multiple devices or delay
initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II
software from the General tab of the Device and Pin Options dialog box.
Supplying a clock on CLKUSR does not affect the configuration process.
The CONF_DONE pin goes high one byte early in parallel configuration
(FPP) modes. The last byte is required for serial configuration (AS and PS)
modes. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as t
devices require 4,436 clock cycles to initialize properly and enter user
mode. Stratix III devices support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device and Pin Options dialog box.
If you use the INIT_DONE pin, it is high because of an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
Stratix III devices receive configuration data on the
DATA[7..0] pins and the clock is received on the DCLK pin.
Data is latched into the device on the rising edge of DCLK. If you
are using the Stratix III decompression and/or design security
feature, configuration data is latched on the rising edge of every
fourth DCLK cycle. After the configuration data is latched in, it is
processed during the following three DCLK cycles.
CD2CU
. After this time period elapses, Stratix III
MAX
of 100 MHz.
Altera Corporation
November 2007