EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 455

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 13–12. BYPASS Shift Data Register Waveforms
Altera Corporation
November 2007
Notes to
(1)
(2)
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Table 13–5. 32-Bit Stratix III Device IDCODE
TAP_STATE
The most significant bit (MSB) is on the left.
The IDCODE’s least significant bit (LSB) is always 1.
TMS
TDO
TCK
TDI
Device
Table
SHIFT_IR
13–5:
Instruction Code
Version (4 Bits)
IDCODE Instruction Mode
Use the IDCODE instruction mode to identify the devices in an IEEE Std.
1149.1 chain. When IDCODE is selected, the device identification register
is loaded with the 32-bit vendor-defined identification code. The device
ID register is connected between the TDI and TDO ports, and the device
IDCODE is shifted out.
Stratix III devices.
EXIT1_IR
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
UPDATE_IR
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
SELECT_DR_SCAN
Part Number (16 Bits)
0010 0001 0000 1000
0010 0001 0000 0001
0010 0001 0000 1001
0010 0001 0000 0010
0010 0001 0000 0011
0010 0001 0000 0101
0010 0001 0000 0110
0010 0001 0000 1010
0010 0001 0000 0111
0010 0001 0000 0100
CAPTURE_DR
Bit 1
Table 13–5
IDCODE (32 Bits)
Bit 2
Bit 1
SHIFT_DR
Data shifted into TDI on
the rising edge of TCK is
shifted out of TDO on the
falling edge of the same
TCK pulse.
Bit 2
Bit 3
shows the IDCODE information for
Stratix III Device Handbook, Volume 1
(1)
Bit 4
Identity (11 Bits)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
Manufacturer
EXIT1_DR
UPDATE_DR
(1 Bit)
LSB
1
1
1
1
1
1
1
1
1
1
13–17
(2)