EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 201

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–36. Delay Insertion Using VCO Phase Output and Counter Delay Time
Altera Corporation
November 2007
CLK0
CLK1
CLK2
135
180
225
270
315
45
90
0
1/8 t
VCO
t
d0-1
t
d0-2
Figure 6–36
resolution using the VCO phase taps method. The eight phases from the
VCO are shown and labeled for reference. For this example, CLK0 is
based off the 0phase from the VCO and has the C value for the counter
set to one. The CLK1 signal is divided by four, two VCO clocks for high
time and two VCO clocks for low time. CLK1 is based off the 135
tap from the VCO and also has the C value for the counter set to one. The
CLK1 signal is also divided by 4. In this case, the two clocks are offset by
3
for the counter set to three. This arrangement creates a delay of 2 Φ
(two complete VCO periods).
You can use the coarse- and fine-phase shifts to implement clock delays
in Stratix III devices.
Stratix III devices support dynamic phase-shifting of VCO phase taps
only. The phase shift is reconfigurable any number of times, and each
phase shift takes about one SCANCLK cycle, allowing you to implement
large phase shifts quickly.
Φ
FINE
t
VCO
. CLK2 is based off the 0phase from the VCO but has the C value
shows an example of phase-shift insertion with the fine
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
°
COARSE
phase
6–51