EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 235

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
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External Memory Interfaces
In addition to the I/O registers in each IOE, Stratix III devices also have
dedicated registers and phase-shift circuitry on all I/O banks for
interfacing with external memory interfaces.
interfaces and the corresponding I/O standards supported by Stratix III
devices.
For more information about external memory interfaces, refer to the
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook.
High-Speed Differential I/O with DPA Support
Stratix III devices contain dedicated circuitry for supporting differential
standards at speeds up to 1.25 Gbps. The high-speed differential I/O
circuitry supports the following high speed I/O interconnect standards
and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSLI,
RapidIO
×10 SERDES modes for high-speed differential I/O interfaces and ×4, ×6,
×7, ×8, and ×10 SERDES modes with dedicated dynamic phase alignment
(DPA) circuitry. DPA minimizes bit errors, simplifies PCB layout and
timing management for high-speed data transfer, and eliminates
channel-to-channel and channel-to-clock skew in high-speed data
transmission systems.
1
Table 7–3. Memory Interface Standards Supported
Memory Interface Standard
TM
×2 mode is supported by the DDR registers and is not included
in SERDES. In Stratix III devices, SERDES can be bypassed in the
Quartus
megafunction to support DDR (×2) operation.
DDR2 SDRAM
DDR3 SDRAM
QDRII+ SRAM
DDR SDRAM
QDRII SRAM
RLDRAM II
, and NPSI. Stratix III devices support ×2, ×4, ×6, ×7, ×8, and
®
II MegaWizard
®
Plug-in Manager for the altlvds
Stratix III Device Handbook, Volume 1
I/O Standard
HSTL-18
HSTL-18
HSTL-15
SSTL-18
SSTL-15
SSTL-2
Stratix III Device I/O Features
Table 7–3
chapter in volume 1 of the
lists the memory
7–17