EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 532

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Switching Characteristics
1–20
Stratix III Device Handbook, Volume 2
f
frequency)
f
f
f
TCCS
SW
t
t
Output t
Output t
t
DPA run length
HSCLK
HSCLK
HSDR
HSDRDPA
OUTPJ_DC
OUTPJ_IO
DUTY
Table 1–24. High Speed I/O Specifications for -2 Speed Grade
(data rate)
(input clock
= f
RISE
FALL
(DPA data rate)
HSDR
Symbol
/ W
Clock boost factor W = 2 to 32
Clock boost factor W = 1 (SERDES bypass)
Clock boost factor W = 1 (SERDES used)
SERDES factor J = 4 to 10
SERDES factor J = 2, Uses DDR Registers
SERDES factor J = 1, Uses SDR Register
All differential I/O standards
All differential I/O standards
All differential I/O standards
All differential I/O standards
tx output clock duty cycle
SERDES factor J = 4 to 10
Periphery Performance
This section describes the periphery performance, including High-Speed
I/O and External Memory Interface, and OCT Calibration Block
specifications.
High-Speed I/O Specifications
Refer to the
specifications.
Table 1–24
shows the high-speed I/O timing for Stratix III devices.
Table 1–206
Conditions
—
—
—
for definitions of high-speed timing
(3)
Notes
(1), (2),
5
5
Min
150
150
150
(4)
(4)
(5)
—
—
—
—
—
45
(5)
(5)
(7)
- Preliminary
Typ
-2 Speed Grade
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Altera Corporation
600
600
1,250
1,250
Max
November 2007
625
717
(5)
(5)
(5)
(5)
(5)
(5)
(5)
55
(5)
(6)
(6)
Mbps
Mbps
Mbps
Mbps
Unit
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
UI
%