EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 181

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
clk[9..0]
PLLs
clk[6..0]
PLLs
clkbad[1..0]
locked
activeclock
scandataout
scandone
phasedone
fbout
Table 6–13. PLL Output Signals
Port
for Top/Bottom
for Left/Right
Table 6–13
PLL output counters driving
regional, global, or external
clocks.
Signals indicating which
reference clock is no longer
toggling.
inclk1
indicates
1= good; 0 = bad
Lock output from lock detect
circuit. Active high
Signal to indicate which clock
(
1 = inclk1
PLL. If this signal is low,
inclk0
signal is high,
the PLL.
Output of the last shift register
in the scan chain.
Signal indicating when the PLL
has completed reconfiguration.
One-to-0 transition indicates
that the PLL has been
reconfigured.
When asserted it indicates that
the phase reconfiguration is
complete and the PLL is ready
to act on a possible second
reconfiguration. Asserts based
on internal PLL timing.
De-asserts on rising edge of
SCANCLK
Output of
clock delay compensation.
0 = inclk0
clkbad1
status,
drives the PLL. If this
inclk0
Description
m
.
shows the PLL output signals for Stratix III devices.
counter. Used for
inclk1
) is driving the
or
clkbad0
status.
indicates
drives
Clock Networks and PLLs in Stratix III Devices
PLL counter
PLL switchover
circuit
PLL lock detect
PLL clock
multiplexer
PLL scan chain
PLL scan chain
PLL scan chain
M counter
Source
Stratix III Device Handbook, Volume 1
Internal or external
clock
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Logic array
Destination
6–31