EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 457

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
I/O standards, you should connect V
I/O standards, you should connect V
board design recommendations to ensure proper JTAG chain operation.
You can interface the TDI and TDO lines of the devices that have different
V
you should build the JTAG chain in such a way that a device with a higher
V
way, a level shifter is used only to shift the TDO level to a level acceptable
to the JTAG tester.
and how a level shifter is inserted in the chain.
Notes to
(1)
(2)
(3)
(4)
Stratix III
Non-Stratix III
Table 13–6. Supported TDO/TDI Voltage Combinations
CCIO
CCIO
Device
The TDO output buffer meets V
The TDO output buffer meets V
Input buffer must be 3.0-V tolerant.
Input buffer must be 2.5-V tolerant.
levels by inserting a level shifter between the devices. If possible,
level drives to a device with an equal or lower V
Table
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
13–6:
TDI Input Buffer Power
V
V
V
V
V
V
CCPD
CCPD
CC
CC
CC
CC
Figure 13–13
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
= 3.0V
= 2.5V
OH
OH
shows the JTAG chain of mixed voltages
(MIN) = 2.4 V.
(MIN) = 2.0 V.
Stratix III Device Handbook, Volume 1
v(1)
v(1)
v(1)
v(1),
v(1),
v(1),
CCPD
CCPD
V
CCPD
to 3.0 V; for 2.5 V and below
to 2.5 V.
(3)
(3)
(3)
Stratix III TDO V
= 3.0 V
Table 13–6
v(2)
v(2)
v(2)
v(2)
v(2),
v(2),
V
CCIO
CCPD
CCPD
(4)
(4)
level. This
= 2.5 V
shows
13–19