EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 417

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
DCLK
DATA0
DATA[7..1]
Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 6 of 6)
Pin Name
User Mode
N/A
I/O
I/O
Configuration
schemes (PS,
Synchronous
configuration
configuration
PS, FPP, AS
FPP, AS)
schemes
Scheme
Parallel
(FPP)
FPP) Output
Input (PS,
Pin Type
Inputs
Input
(AS)
In PS and FPP configuration,
clock input used to clock data from an external
source into the target device. Data is latched
into the device on the rising edge of
In AS mode,
Stratix III device that provides timing for the
configuration interface. In AS mode,
an internal pull-up resistor (typically 25 kΩ)
that is always active.
After configuration, this pin is tri-stated. In
schemes that use a configuration device,
DCLK
done. In schemes that use a control host,
DCLK
whichever is more convenient. Toggling this
pin after configuration does not affect the
configured device.
Data input. In serial configuration modes,
bit-wide configuration data is presented to the
target device on the
In AS mode,
resistor that is always active.
After configuration,
user I/O pin and the state of this pin depends
on the Dual-Purpose Pin settings.
Data inputs. Byte-wide configuration data is
presented to the target device on
DATA[7..0]
In serial configuration schemes, they function
as user I/O pins during configuration, which
means they are tri-stated.
After FPP configuration,
available as user I/O pins and the state of
these pin depends on the Dual-Purpose Pin
settings.
Stratix III Device Handbook, Volume 1
will be driven low after configuration is
should be driven either high or low,
DCLK
DATA0
Configuring Stratix III Devices
.
Description
is an output from the
DATA0
DATA0
has an internal pull-up
DATA[7..1]
is available as a
pin.
DCLK
DCLK
is the
DCLK
are
11–57
has
.