EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 223

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III I/O
Banks
Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
Differential
HSTL-12 Class I
Differential
HSTL-12 Class II
LVDS (3),
RSDS (5),
mini-LVDS (5),
(6)
LVPECL
Table 7–2. Stratix III I/O Standards and Voltage Levels
I/O Standard
V
For 2.5 V and below I/O standards, V
Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by V
Column I/O banks support LVPECL I/O standards for input clock operation. Differential clock inputs in column
I/O use V
Column I/O banks support LVDS outputs using two single-ended output buffers and external one-resistor
(LVDS_E_1R) and a three-resistor (LVDS_E_3R) network.
Row I/O banks support RSDS and mini-LVDS I/O standards using a dedicated LVDS output buffer without a
resistor network.
Column I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with
one-resistor (RSDS_E_1R and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
CCPD
Table
(4)
(6)
is either 2.5 V, 3.0 V, or 3.3 V. For a 3.3-V I/O standard, V
7–2:
CCCLKIN
f
ANSI/TIA/
Standard
Support
EIA-644
JESD8-
JESD8-
.
16A
16A
—
—
—
Refer to the
in volume 2 of the Stratix III Device Handbook for detailed electrical
characteristics of each I/O standard.
Stratix III devices contain up to 24 I/O banks, as shown in
row I/O banks contain true differential input and output buffers and
dedicated circuitry to support differential standards at speeds up to
1.25 Gbps.
Every I/O bank in Stratix III devices can support high-performance
external memory interfaces with dedicated circuitry. The I/O pins are
organized in pairs to support differential standards. Each I/O pin pair
can support both differential input and output buffers. The only
Bottom I/O
Top and
Banks
Input Operation
(2)
(2)
(2)
(2)
(2)
(3)
CCPD
DC and Switching Characteristics of Stratix III Devices
Right I/O
Left and
= 2.5 V.
Banks
(2)
(2)
(2)
(2)
(2)
—
V
CCIO
Notes
(V)
Bottom I/O
Top and
Banks
Output Operation
N/A
1.2
1.2
2.5
2.5
2.5
(1),
CCPD
(2)
Stratix III Device Handbook, Volume 1
=3.3 V. For a 3.0-V I/O standard, V
Right I/O
Left and
(Part 3 of 3)
Banks
N/A
N/A
1.2
2.5
2.5
2.5
Stratix III Device I/O Features
V
Voltage)
CCPD
Driver
(Pre-
2.5
2.5
2.5
2.5
2.5
—
(V)
Figure
Voltage)
V
(Input
REF
Ref
N/A
N/A
N/A
N/A
N/A
N/A
CCPD
(V)
chapter
7–1. The
.
Termination
CCPD
7–5
Voltage)
(Board
V
0.60
0.60
TT
N/A
N/A
N/A
N/A
= 3.0 V.
(V)