EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 114

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

DSP Block Resource Descriptions
5–14
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Parallel input
Shift register input
Loopback input
Table 5–3. Input Register Modes
Register Input Mode
The multiplier operand input wordlengths are statically configured at compile time.
Available only on the A-operand.
Only one loopback input is allowed per Half-Block. See
Table
5–3:
(3)
(2)
(1)
You must select whether the A-input comes from general routing or from
the cascade chain at compile time. In cascade mode, the dedicated shift
outputs from one multiplier block directly feeds input registers of the
adjacent multiplier below it (within the same half DSP block) or the first
multiplier in the next half DSP block, to form an 8-tap shift register chain
per DSP Block. The DSP block can increase the length of the shift register
chain by cascading to the lower DSP blocks. The dedicated shift register
chain spans a single column, but you can implement longer shift register
chains requiring multiple columns using the regular FPGA routing
resources.
Shift registers are useful in DSP functions such as FIR filters. When
implementing 18 × 18 or smaller width multipliers, you do not need
external logic to create the shift register chain because the input shift
registers are internal to the DSP block. This implementation significantly
reduces the logical element (LE) resources required, avoids routing
congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in
Stratix III devices has a mux for the first multiplier B-input (lower-leg
input) register to select between general routing and loopback, as shown
in
outputs are connected as feedback to the multiplier input of the first top
multiplier in each half DSP block. Loopback modes are used by recursive
filters where the previous output is needed to compute the current
output.
The loopback mode is described in detail in
Mode” on page
Table 5–3
Figure
9 × 9
v
—
—
5–6. In loopback mode, the most significant 18-bit registered
shows the summary of input register modes for the DSP block.
5–25.
12 × 12
v
—
—
Figure 5–15
18 × 18
for details.
v
v
v
“Two-Multiplier Adder Sum
36 × 36
v
—
—
Altera Corporation
October 2007
Double
v
—
—