HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 940

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 User Break Controller (UBC)
20.2
20.2.1
The access size must be the same as the control register size. If the sizes are different, a write will
not be effected in a UBC register write operation, and a read operation will return an undefined
value. UBC control register contents cannot be transferred to a floating-point register using a
floating-point memory load instruction.
When a UBC control register is updated, use either of the following methods to make the updated
value valid:
1. Execute an RTE instruction after the memory store instruction that updated the register. The
2. Execute instructions requiring 5 states for execution after the memory store instruction that
Rev.7.00 Oct. 10, 2008 Page 854 of 1074
REJ09B0366-0700
updated value will be valid from the RTE instruction jump destination onward.
updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5
state is required for execution of one instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
Register Descriptions
Access to UBC Control Registers