HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 447

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
0
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Name
Data enable 0
Data enable 1
Data enable 2
Data enable 3
Data enable 4
WE0/CAS0/
DQM0
WE1/CAS1/
DQM1
WE2/CAS2/
DQM2/ICIORD
WE3/CAS3/
DQM3/ICIOWR
WE4/CAS4/
DQM4
Signals
I/O
O
O
O
O
O
Description
When setting synchronous DRAM interface:
selection signal for D7–D0
When setting DRAM interface: CAS signal for
D7–D0
When setting MPX interface: high-level output
In other cases: write strobe signal for D7–D0
When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: CAS signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: CAS signal for
D23–D16
When setting PCMCIA interface: ICIORD signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
When setting synchronous DRAM interface:
selection signal for D31–D24
When setting DRAM interface: CAS signal for
D31–D24
When setting PCMCIA interface: ICIOWR signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
When setting synchronous DRAM interface:
selection signal for D39–D32
When setting DRAM interface: CAS signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
Rev.7.00 Oct. 10, 2008 Page 361 of 1074
Section 13 Bus State Controller (BSC)
REJ09B0366-0700

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