HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 212

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
Note: This includes a break triggered by a debugging tool swapping an instruction (a break
Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or
Description: When the problem occurs, 8 bytes of incorrect data is written to the 8-byte boundary
that includes an address that differs by H'2000 from the address accessed by the store instruction
that accesses internal RAM mentioned in condition 4. For example, when a long word is stored at
address H'7C000204, the 8 bytes of data in the internal RAM mapped to addresses H'7C002200 to
H'7C002207 becomes corrupted.
Examples
Example 1 A store instruction accessing internal RAM occurs within four instructions after an
MOV.L #H'0C400000, R0
MOV.L #H'7C000204, R1
MOV.L @R0, R2
NOP
NOP
NOP
MOV.L R3, @R1
Example 2 A store instruction accessing internal RAM occurs within four instructions after an
MOV.L #H'7C002000, R1
MOV.L #H'12345678, R0
NOP
NOP
NOP
MOV.L R0, @R1
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REJ09B0366-0700
occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped
for an instruction).
instruction generating a TLB miss exception.
instruction causing an interrupt to be accepted.
STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four
instructions after the instruction associated with the exception or interrupt described
in condition 3. This includes cases where the store instruction that accesses internal
RAM itself generates an exception.
R0 is an address causing a TLB miss.
R1 is an address mapped to internal RAM.
TLB miss exception occurs.
1st word
2nd word
3rd word
Store instruction accessing internal RAM
R1 is an address mapped to internal RAM.
An interrupt is accepted after this instruction.
1st word
2nd word
3rd word
Store instruction accessing internal RAM