HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 257

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
0
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(8) Unconditional Trap
• Source: Execution of TRAPA instruction
• Transition address: VBR + H'0000 0100
• Transition operations:
TRAPA_exception()
{
}
As this is a processing-completion-type exception, the PC contents for the instruction
following the TRAPA instruction are saved in SPC. The values of SR and R15 when the
TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the
TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160
is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =
VBR + H'0100.
SPC = PC + 2;
SSR = SR;
SGR = R15;
TRA = imm << 2;
EXPEVT = H'00000160;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
Rev.7.00 Oct. 10, 2008 Page 171 of 1074
Section 5 Exceptions
REJ09B0366-0700

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