HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 359
HD6417750SBP200
Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417750RBP240DV.pdf
(1164 pages)
Specifications of HD6417750SBP200
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 359 of 1164
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Bit
CSTP1 *
CSTP0 *
MSTP6 *
MSTP5 *
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
Notes: 1. The register initialized is the same as in standby mode, but initialization is not
9.6.2
The module standby function is exited by clearing the MSTP6–MSTP0, CSTP1, and CSTP0 bits
to 0, or by a power-on reset via the RESET pin or a power-on reset caused by watchdog timer
overflow.
2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
3. Terminate DMA transfers prior to making the transition to module standby mode. If you
4. SH7750S, SH7750R only
5. For details, see section 20.6, User Break Controller Stop Function.
6. SH7750R only
6
6
4
4
Exit from Module Standby Function
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
Clock (RTC)).
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Peripheral clock is supplied to TMU channels 3 and 4
Peripheral clock supplied to TMU channels 3 and 4 is stopped
INTC detects interrupts on TMU channels 3 and 4
INTC does not detect interrupts on TMU channels 3 and 4
SQ operates
Clock supplied to SQ is stopped
UBC operates
Clock supplied to UBC is stopped *
DMAC operates
Clock supplied to DMAC is stopped *
SCIF operates
Clock supplied to SCIF is stopped
TMU operates
Clock supplied to TMU is stopped, and register is initialized *
RTC operates
Clock supplied to RTC is stopped *
SCI operates
Clock supplied to SCI is stopped
Rev.7.00 Oct. 10, 2008 Page 273 of 1074
2
5
3
Section 9 Power-Down Modes
REJ09B0366-0700
1
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