HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 478

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait
states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 31: A6W2
0
1
Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Bit 28: A6B2
0
1
Rev.7.00 Oct. 10, 2008 Page 392 of 1074
REJ09B0366-0700
Bit 30: A6W1
0
1
0
1
Bit 27: A6B1
0
1
0
1
Bit 29: A6W0
0
1
0
1
0
1
0
1
Bit 26: A6B0
0
1
0
1
0
1
0
1
0
1
2
3
6
9
12
15 (Initial value)
Wait States Inserted from
Second Data Access
Onward
0
1
2
3
4
5
6
7 (Initial value)
Inserted Wait States
Burst Cycle (Excluding First Cycle)
Description
Description
First Cycle
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled