HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 691

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5.2
Figure 14.24 shows the system configuration in DDT mode.
• DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR
• BAVL: Data bus D63–D0 release signal
• TR: Transfer request signal
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL.
Assertion of BAVL means that the data bus will be released two cycles later.
This LSI does not switch the data pins to output status for a total of three cycles: the cycle in
which the data bus is released and the cycles preceding and following it.
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same
⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a
A25–A0, RAS, CAS, WE, DQMn, CKE
time the DTR format is output, two cycles after BAVL is asserted.
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when BAVL is not asserted two cycles
earlier.
SH7750, SH7750S, SH7750R
Pins in DDT Mode
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D63–D0=DTR
Synchronous
DRAM
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 605 of 1074
External device
REJ09B0366-0700