HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 649

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1.
Bit 1: TE
0
1
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel.
Bit 0: DE
0
1
When auto-request is specified (with RS3–RS0), transfer is begun when this bit is set to 1. In the
case of an external request or on-chip peripheral module request, transfer is begun when a transfer
request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to
0.
Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0,
or when the NMIF or AE bit in DMAOR is 1.
For channel 0, in DDT mode this bit is set to 1 when a DTR format is received. DE remains set to
1 even if TE is set to 1. When the mode is switched from DDT mode to normal DMA mode (DDT
bit = 0 in DMAOR), the DE bit must be cleared to 0.
Description
Number of transfers specified in DMATCR not completed
[Clearing conditions]
•
•
Number of transfers specified in DMATCR completed
Description
Operation of corresponding channel is disabled
Operation of corresponding channel is enabled
When 0 is written to TE after reading TE = 1
In a power-on or manual reset, and in standby mode
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 563 of 1074
REJ09B0366-0700
(Initial value)
(Initial value)