HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 352

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Power-Down Modes
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
0
1
Note:
Bit 6—STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0
and STATUS1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot
be guaranteed if 1 is written. These bits are always read as 0.
Bit 1 (SH7750S and SH7750R)—Module Stop 6 (MSTP6): Specifies that the clock supply to
the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops
the clock supply to the SQ, and the SQ functions are therefore unavailable.
Bit 1: MSTP6
0
1
Bit 0 (SH7750S and SH7750R)—Module Stop 5 (MSTP5): Specifies stopping of the clock
supply to the user break controller (UBC) among the on-chip peripheral modules. See section
20.6, User Break Controller Stop Function, for how to set the clock supply.
Bit 0: MSTP5
0
1
Rev.7.00 Oct. 10, 2008 Page 266 of 1074
REJ09B0366-0700
*
When the STBY bit in the STBCR register is 0
Description
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
Transition to deep sleep mode on execution of SLEEP instruction*
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
Drives STATUS0, 1 pins to LH when in hardware standby mode
Description
SQ operating
Clock supply to SQ stopped
Description
UBC operating
Clock supply to UBC stopped
(Initial value)
(Initial value)
(Initial value)