HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 202

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
• CB: Copy-back bit
• WT: Write-through bit
• OCE: OC enable bit
Notes: 1. No compatibility for RAM mode in OC index mode and address assignment in RAM
(2) Queue Address Control Register 0 (QACR0): Longword access to QACR0 can be
performed from H'FF00 0038 in the P4 area and H'1F00 0038 in area 7. QACR0 specifies the area
onto which store queue 0 (SQ0) is mapped when the MMU is off.
(3) Queue Address Control Register 1 (QACR1): Longword access to QACR1 can be
performed from H'FF00 003C in the P4 area and H'1F00 003C in area 7. QACR1 specifies the
area onto which store queue 1 (SQ1) is mapped when the MMU is off.
4.3
4.3.1
The operand cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 512
cache lines, each composed of a 19-bit tag, V bit, U bit, and 32-byte data. The SH7750R's operand
cache is 2-way set-associative. Each way consists of 512 cache lines.
Figure 4.2 shows the configuration of the operand cache for the SH7750 and SH7750S.
Rev.7.00 Oct. 10, 2008 Page 116 of 1074
REJ09B0366-0700
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
Indicates the P0, U0, and P3 area cache write mode. When address translation is performed,
the value of the WT bit in the page management information has priority.
0: Copy-back mode
1: Write-through mode
Indicates whether or not the OC is to be used. When address translation is performed, the OC
cannot be used unless the C bit in the page management information is also 1.
0: OC not used
1: OC used
2. When the ORA bit is 1 in the SH7750R, the OIX bit should be cleared to 0.
3. When the OIX bit in the SH7750R is 1, the ORA bit should be cleared to 0.
Operand Cache (OC)
Configuration
mode.