HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 916

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
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Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 19 Interrupt Controller (INTC)
Table 19.3 IRL3–IRL0 Pins and Interrupt Levels
IRL3
0
1
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no
transient level on the IRL pin change is detected. In standby mode, as the bus clock is stopped,
noise cancellation is performed using the 32.768 kHz clock for the RTC instead. When the RTC is
not used, therefore, interruption by means of IRL interrupts cannot be performed in standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt
handling.
Pins IRL0–IRL3 can be used for four independent interrupt requests by setting the IRLM bit to 1
in the ICR register. When independent interrupt requests are used in the SH7750, the interrupt
priority levels are fixed (table 19.4). When independent interrupt requests are used in the SH7750S
or SH7750R, the interrupt priority levels can be set in interrupt priority register D (IPRD).
Rev.7.00 Oct. 10, 2008 Page 830 of 1074
REJ09B0366-0700
IRL2
0
1
0
1
IRL1
0
1
0
1
0
1
0
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request

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