HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 78

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait),
Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait)
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address
Figure 22.61 TCLK Input Timing .............................................................................................. 1011
Figure 22.62 RTC Oscillation Settling Time at Power-On......................................................... 1011
Figure 22.63 SCK Input Clock Timing ...................................................................................... 1011
Figure 22.64 SCI I/O Synchronous Mode Clock Timing ........................................................... 1012
Figure 22.65 I/O Port Input/Output Timing................................................................................ 1012
Figure 22.66 (a) DREQ/DRAK Timing.................................................................................... 1012
Figure 22.66 (b) DBREQ/TR Input Timing and BAVL Output Timing .................................. 1013
Figure 22.67 TCK Input Timing................................................................................................. 1013
Figure 22.68 RESET Hold Timing............................................................................................. 1014
Figure 22.69 H-UDI Data Transfer Timing................................................................................ 1014
Figure 22.70 Pin Break Timing .................................................................................................. 1014
Figure 22.71 NMI Input Timing................................................................................................. 1014
Figure 22.72 Output Load Circuit .............................................................................................. 1015
Figure 22.73 Load Capacitance vs. Delay Time......................................................................... 1016
Appendix B Package Dimensions
Figure B.1
Figure B.2
Figure B.3
Figure B.4
Appendix D CKIO2ENB Pin Configuration
Figure D.1
Appendix G Prefetching of Instructions and its Side Effects
Figure G.1
Appendix H Power-On and Power-Off Procedures
Figure H.1
Figure H.2
Rev.7.00 Oct. 10, 2008 Page lxxvi of lxxxiv
REJ09B0366-0700
2nd to 4th Data (No Internal Wait + External Wait Control) ................................ 1000
(2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal
Wait + One External Wait).................................................................................... 1001
Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =0 1) ..................................... 1002
Package Dimensions (256-Pin BGA).................................................................... 1023
Package Dimensions (208-Pin QFP) ..................................................................... 1024
Package Dimensions (264-Pin CSP) ..................................................................... 1025
Package Dimensions (292-Pin BGA).................................................................... 1026
CKIO2ENB Pin Configuration ............................................................................. 1031
Instruction Prefetch ............................................................................................... 1059
Power-On Procedure 1 .......................................................................................... 1062
Power-On Procedure 2 .......................................................................................... 1063