HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 567

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D63–D0
(read)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.37 Burst Write Timing (Different Row Addresses)
Tpr
Row
H/L
Tpc
Tr
Row
Row
Row
Trw
Tc1
c1
Tc2
Rev.7.00 Oct. 10, 2008 Page 481 of 1074
c2
Section 13 Bus State Controller (BSC)
H/L
c1
Tc3
c3
Tc4
c4
Trwl
REJ09B0366-0700
Trwl
Trwl