HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 575

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state
controller provides for value X to be written to the synchronous DRAM mode register by
performing a write to address H'FF900000 + X for area 2 synchronous DRAM, and to address
H'FF940000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the
mode write is performed as a byte-size access. To set burst read/write, CAS latency 1 to 3, wrap
type = sequential, and burst length 4* or 8, supported by this LSI, arbitrary data is written by byte-
size access to the following addresses.
Bus Width
32
32
64
Note:
The value set in MCR.MRSET is used to select whether a precharge all banks command or a mode
register setting command is issued. The timing for the precharge all banks command is shown in
figure 13.42 (1), and the timing for the mode register setting command in figure 13.42 (2).
Before mode register, a 200 µs idle time (depending on the memory manufacturer) must be
guaranteed after the power required for the synchronous DRAM is turned on. If the reset signal
pulse width is greater than this idle time, there is no problem in making the precharge all banks
setting immediately.
First, a precharge all banks (PALL) command is issued in the TRp1 cycle by performing a write to
address H'FF900000 + X or H'FF940000 + X while MCR.MRSET = 0. Next, the number of
dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed.
This is achieved automatically while various kinds of initialization are being performed after auto-
refresh setting, but a way of carrying this out more dependably is to change the RTCOR register
*
SH7750R only.
Burst Length
4*
8
4
CAS Latency
1
2
3
1
2
3
1
2
3
Rev.7.00 Oct. 10, 2008 Page 489 of 1074
Area 2
H'FF900048
H'FF900088
H'FF9000C8
H'FF90004C
H'FF90008C
H'FF9000CC
H'FF900090
H'FF900110
H'FF900190
Section 13 Bus State Controller (BSC)
Area 3
H'FF940048
H'FF940088
H'FF9400C8
H'FF94004C
H'FF94008C
H'FF9400CC
H'FF940090
H'FF940110
H'FF940190
REJ09B0366-0700