HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 461

IC SUPERH MPU ROMLESS 256BGA

HD6417750SBP200

Manufacturer Part Number
HD6417750SBP200
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750SBP200

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 2.07 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750SBP200
Manufacturer:
HITACHI
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Part Number:
HD6417750SBP200
Manufacturer:
RENESAS/瑞萨
Quantity:
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Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 20: A4MBC
0
1
Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.
BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is
ignored in the case of a slave mode startup.
Bit 19: BREQEN
0
1
Bit 18—Partial-Sharing Bit (PSHR): Sets partial-sharing mode. PSHR is valid only in the case
of a master mode startup.
Bit 18: PSHR
0
1
Bit 17—Area 1 to 6 MPX Interface Specification (MEMMPX): Sets the MPX interface when
areas 1 to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a
power-on reset.
Bit 17: MEMMPX
0
1
Description
Area 4 SRAM is set to normal mode
Area 4 SRAM is set to byte control mode
Description
External requests are not accepted
External requests are accepted
Description
Master mode
Partial-sharing mode
Description
SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are
set as SRAM interface (or burst ROM interface)
MPX interface is selected when areas 1 to 6 are set as SRAM interface (or
burst ROM interface)
Rev.7.00 Oct. 10, 2008 Page 375 of 1074
Section 13 Bus State Controller (BSC)
REJ09B0366-0700
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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