HD6417750SBP200 Renesas Electronics America, HD6417750SBP200 Datasheet - Page 441

• Manufacturer Part Number: HD6417750SBP200
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SBP200

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 2.07 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12.4
There are four TMU interrupt sources, comprising underflow interrupts and the input capture
interrupt (when the input capture function is used). Underflow interrupts are generated on each of
the channels, and input capture interrupts on channel 2 only.
An underflow interrupt request is generated (for each channel) when the UNF bit in TCR is 1 and
the interrupt enable bit for the corresponding channel is 1.
When the input capture function is used and an input capture request is generated, an interrupt is
requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits
(ICPE1, ICPE0) in TCR2 are 11.
The TMU interrupt sources are summarized in table 12.3.
Table 12.3 TMU Interrupt Sources
Channel
0
1
2
3*
4*
Note:
12.5
12.5.1
When performing a register write, timer count operation must be stopped by clearing the start bit
(STR0–STR4) for the relevant channel in the timer start register (TSTR, TSTR2).
Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF)
and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while
the count is in progress. When the flags (UNF, ICPF) are cleared while the count is in progress,
make sure not to change the values of bits other than those being cleared.
*
Interrupts
Usage Notes
Register Writes
SH7750R only
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
TUNI3
TUNI4
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Underflow interrupt 3
Underflow interrupt 4
Rev.7.00 Oct. 10, 2008 Page 355 of 1074
Section 12 Timer Unit (TMU)
Priority
High
Low
REJ09B0366-0700